📄 eclock.rpt
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_EQ051 = !_LC2_C8 & _LC6_C8
# _LC6_C8 & !_LC8_C8
# _LC2_C8 & !_LC6_C8 & _LC8_C8;
-- Node name is '|count60:11|74161:1|f74161:sub|:110' = '|count60:11|74161:1|f74161:sub|QD'
-- Equation name is '_LC4_C8', type is buried
_LC4_C8 = DFFE( _EQ052, GLOBAL( clk), _LC5_C8, VCC, VCC);
_EQ052 = !_LC2_C8 & _LC4_C8
# _LC4_C8 & !_LC8_C8
# _LC4_C8 & !_LC6_C8
# _LC2_C8 & !_LC4_C8 & _LC6_C8 & _LC8_C8;
-- Node name is '|count60:11|74161:2|f74161:sub|:9' = '|count60:11|74161:2|f74161:sub|QA'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = DFFE(!_LC3_C9, !_LC3_C8, _LC5_C9, VCC, VCC);
-- Node name is '|count60:11|74161:2|f74161:sub|:87' = '|count60:11|74161:2|f74161:sub|QB'
-- Equation name is '_LC4_C9', type is buried
_LC4_C9 = DFFE( _EQ053, !_LC3_C8, _LC5_C9, VCC, VCC);
_EQ053 = _LC3_C9 & !_LC4_C9
# !_LC3_C9 & _LC4_C9;
-- Node name is '|count60:11|74161:2|f74161:sub|:99' = '|count60:11|74161:2|f74161:sub|QC'
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = DFFE( _EQ054, !_LC3_C8, _LC5_C9, VCC, VCC);
_EQ054 = !_LC3_C9 & _LC6_C9
# !_LC4_C9 & _LC6_C9
# _LC3_C9 & _LC4_C9 & !_LC6_C9;
-- Node name is '|count60:11|74161:2|f74161:sub|:110' = '|count60:11|74161:2|f74161:sub|QD'
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = DFFE( _EQ055, !_LC3_C8, _LC5_C9, VCC, VCC);
_EQ055 = _LC2_C9 & !_LC6_C9
# _LC2_C9 & !_LC3_C9
# _LC2_C9 & !_LC4_C9
# !_LC2_C9 & _LC3_C9 & _LC4_C9 & _LC6_C9;
-- Node name is '|count60:12|:6'
-- Equation name is '_LC6_C12', type is buried
!_LC6_C12 = _LC6_C12~NOT;
_LC6_C12~NOT = LCELL( _EQ056);
_EQ056 = _LC3_C6 & _LC5_C6;
-- Node name is '|count60:12|:31'
-- Equation name is '_LC6_C6', type is buried
_LC6_C6 = LCELL( _EQ057);
_EQ057 = clr & !_LC5_C6
# clr & !_LC3_C6;
-- Node name is '|count60:12|:32'
-- Equation name is '_LC5_C12', type is buried
_LC5_C12 = LCELL( _EQ058);
_EQ058 = clr & _LC3_C12
# clr & !_LC4_C12
# clr & !_LC1_C12;
-- Node name is '|count60:12|74161:1|f74161:sub|:9' = '|count60:12|74161:1|f74161:sub|QA'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = DFFE(!_LC4_C6, _LC1_C9, _LC6_C6, VCC, VCC);
-- Node name is '|count60:12|74161:1|f74161:sub|:87' = '|count60:12|74161:1|f74161:sub|QB'
-- Equation name is '_LC5_C6', type is buried
_LC5_C6 = DFFE( _EQ059, _LC1_C9, _LC6_C6, VCC, VCC);
_EQ059 = !_LC4_C6 & _LC5_C6
# _LC4_C6 & !_LC5_C6;
-- Node name is '|count60:12|74161:1|f74161:sub|:99' = '|count60:12|74161:1|f74161:sub|QC'
-- Equation name is '_LC7_C6', type is buried
_LC7_C6 = DFFE( _EQ060, _LC1_C9, _LC6_C6, VCC, VCC);
_EQ060 = !_LC5_C6 & _LC7_C6
# !_LC4_C6 & _LC7_C6
# _LC4_C6 & _LC5_C6 & !_LC7_C6;
-- Node name is '|count60:12|74161:1|f74161:sub|:110' = '|count60:12|74161:1|f74161:sub|QD'
-- Equation name is '_LC3_C6', type is buried
_LC3_C6 = DFFE( _EQ061, _LC1_C9, _LC6_C6, VCC, VCC);
_EQ061 = _LC3_C6 & !_LC5_C6
# _LC3_C6 & !_LC4_C6
# _LC3_C6 & !_LC7_C6
# !_LC3_C6 & _LC4_C6 & _LC5_C6 & _LC7_C6;
-- Node name is '|count60:12|74161:2|f74161:sub|:9' = '|count60:12|74161:2|f74161:sub|QA'
-- Equation name is '_LC3_C12', type is buried
_LC3_C12 = DFFE(!_LC3_C12, !_LC6_C12, _LC5_C12, VCC, VCC);
-- Node name is '|count60:12|74161:2|f74161:sub|:87' = '|count60:12|74161:2|f74161:sub|QB'
-- Equation name is '_LC4_C12', type is buried
_LC4_C12 = DFFE( _EQ062, !_LC6_C12, _LC5_C12, VCC, VCC);
_EQ062 = _LC3_C12 & !_LC4_C12
# !_LC3_C12 & _LC4_C12;
-- Node name is '|count60:12|74161:2|f74161:sub|:99' = '|count60:12|74161:2|f74161:sub|QC'
-- Equation name is '_LC1_C12', type is buried
_LC1_C12 = DFFE( _EQ063, !_LC6_C12, _LC5_C12, VCC, VCC);
_EQ063 = _LC1_C12 & !_LC3_C12
# _LC1_C12 & !_LC4_C12
# !_LC1_C12 & _LC3_C12 & _LC4_C12;
-- Node name is '|count60:12|74161:2|f74161:sub|:110' = '|count60:12|74161:2|f74161:sub|QD'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = DFFE( _EQ064, !_LC6_C12, _LC5_C12, VCC, VCC);
_EQ064 = _LC2_C12 & !_LC3_C12
# _LC2_C12 & !_LC4_C12
# !_LC1_C12 & _LC2_C12
# _LC1_C12 & !_LC2_C12 & _LC3_C12 & _LC4_C12;
-- Node name is '|7448:49|:69' = '|7448:49|OA'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = LCELL( _EQ065);
_EQ065 = !_LC1_C10 & _LC2_C11 & _LC6_C5
# !_LC1_C1 & !_LC1_C10 & _LC2_C11
# !_LC1_C1 & !_LC2_C11 & !_LC6_C5
# !_LC1_C1 & !_LC1_C10 & !_LC6_C5
# _LC1_C10 & !_LC2_C11 & _LC6_C5
# !_LC1_C1 & _LC1_C10 & !_LC2_C11
# _LC1_C1 & !_LC2_C11 & _LC6_C5
# _LC1_C1 & !_LC1_C10 & _LC6_C5;
-- Node name is '|7448:49|:68' = '|7448:49|OB'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = LCELL( _EQ066);
_EQ066 = !_LC1_C10 & !_LC6_C5
# _LC1_C10 & !_LC2_C11 & _LC6_C5
# !_LC1_C1 & !_LC2_C11
# !_LC1_C1 & !_LC1_C10;
-- Node name is '|7448:49|:70' = '|7448:49|OC'
-- Equation name is '_LC7_B5', type is buried
_LC7_B5 = LCELL( _EQ067);
_EQ067 = !_LC2_C11 & _LC6_C5
# !_LC1_C1 & _LC6_C5
# !_LC1_C10 & !_LC2_C11
# !_LC1_C1 & !_LC1_C10
# _LC1_C1 & !_LC2_C11;
-- Node name is '|7448:49|:67' = '|7448:49|OD'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ068);
_EQ068 = _LC1_C10 & !_LC6_C5
# !_LC1_C1 & _LC1_C10
# _LC1_C1 & !_LC1_C10 & _LC6_C5
# !_LC1_C1 & !_LC6_C5;
-- Node name is '|7448:49|:71' = '|7448:49|OE'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = LCELL( _EQ069);
_EQ069 = _LC1_C10 & !_LC6_C5
# !_LC1_C1 & !_LC6_C5;
-- Node name is '|7448:49|:66' = '|7448:49|OF'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = LCELL( _EQ070);
_EQ070 = !_LC1_C10 & _LC2_C11
# !_LC1_C10 & !_LC6_C5
# _LC1_C1 & !_LC6_C5
# _LC1_C1 & !_LC1_C10;
-- Node name is '|7448:49|:72' = '|7448:49|OG'
-- Equation name is '_LC6_B5', type is buried
_LC6_B5 = LCELL( _EQ071);
_EQ071 = _LC1_C10 & !_LC6_C5
# !_LC1_C1 & _LC1_C10
# _LC1_C1 & !_LC6_C5
# _LC1_C1 & !_LC1_C10
# _LC2_C11 & !_LC6_C5
# !_LC1_C10 & _LC2_C11
# !_LC1_C1 & _LC2_C11;
-- Node name is '~35~1'
-- Equation name is '~35~1', location is LC8_C6, type is buried.
-- synthesized logic cell
_LC8_C6 = LCELL( _EQ072);
_EQ072 = clk & !_LC3_C6 & !_LC7_C6 & spclk;
-- Node name is '~35~2'
-- Equation name is '~35~2', location is LC2_C6, type is buried.
-- synthesized logic cell
_LC2_C6 = LCELL( _EQ073);
_EQ073 = !_LC2_C12 & !_LC4_C6 & !_LC5_C6 & _LC8_C6;
-- Node name is ':35'
-- Equation name is '_LC8_C12', type is buried
_LC8_C12 = LCELL( _EQ074);
_EQ074 = !_LC1_C12 & _LC2_C6 & !_LC3_C12 & !_LC4_C12;
-- Node name is ':38'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = LCELL( _EQ075);
_EQ075 = !_LC3_C9 & _LC4_C9 & _LC6_C9 & !setm
# !_LC6_C9 & setm
# !_LC4_C9 & setm
# _LC3_C9 & setm;
-- Node name is ':39'
-- Equation name is '_LC6_C7', type is buried
_LC6_C7 = LCELL( _EQ076);
_EQ076 = _LC1_C12 & !_LC3_C12 & _LC4_C12 & !seth
# _LC3_C12 & seth
# !_LC4_C12 & seth
# !_LC1_C12 & seth;
-- Node name is ':50'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = LCELL( _EQ077);
_EQ077 = _LC3_C2
# _LC5_C2;
Project Information f:\maxplus_study\tt\eclock\eclock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,935K
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