📄 eclock.rpt
字号:
25 - - B -- OUTPUT 0 1 0 0 dop
22 - - B -- OUTPUT 0 1 0 0 ee
23 - - B -- OUTPUT 0 1 0 0 ff
24 - - B -- OUTPUT 0 1 0 0 gg
3 - - - 12 OUTPUT 0 1 0 0 speaker
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\maxplus_study\tt\eclock\eclock.rpt
eclock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 04 DFFE + 0 3 1 0 |CHOICE6:34|:26
- 5 - C 02 DFFE + 0 1 1 1 |CHOICE6:34|:28
- 2 - C 01 DFFE + 0 1 1 0 |CHOICE6:34|:30
- 3 - C 02 DFFE + 0 1 1 1 |CHOICE6:34|:32
- 6 - C 03 DFFE + 0 2 1 0 |CHOICE6:34|:34
- 2 - C 03 DFFE + 0 2 1 0 |CHOICE6:34|:36
- 2 - C 11 DFFE + 0 3 0 5 |CHOICE6:34|kk3 (|CHOICE6:34|:43)
- 1 - C 01 DFFE + 0 3 0 7 |CHOICE6:34|kk2 (|CHOICE6:34|:44)
- 1 - C 10 DFFE + 0 3 0 7 |CHOICE6:34|kk1 (|CHOICE6:34|:45)
- 6 - C 05 DFFE + 0 3 0 7 |CHOICE6:34|kk0 (|CHOICE6:34|:46)
- 7 - C 04 DFFE + 0 2 0 8 |CHOICE6:34|qqq2 (|CHOICE6:34|:47)
- 6 - C 04 DFFE + 0 2 0 8 |CHOICE6:34|qqq1 (|CHOICE6:34|:48)
- 8 - C 10 DFFE + 0 2 0 9 |CHOICE6:34|qqq0 (|CHOICE6:34|:49)
- 2 - C 04 OR2 ! 0 3 0 6 |CHOICE6:34|:350
- 3 - C 11 OR2 0 3 0 1 |CHOICE6:34|:353
- 5 - C 04 AND2 0 3 0 5 |CHOICE6:34|:360
- 4 - C 11 OR2 0 3 0 1 |CHOICE6:34|:363
- 3 - C 04 OR2 ! 0 3 0 8 |CHOICE6:34|:370
- 5 - C 11 OR2 0 3 0 1 |CHOICE6:34|:373
- 4 - C 04 AND2 0 3 0 6 |CHOICE6:34|:380
- 6 - C 11 OR2 0 3 0 1 |CHOICE6:34|:383
- 2 - C 02 OR2 ! 0 3 0 6 |CHOICE6:34|:390
- 7 - C 11 OR2 0 3 0 1 |CHOICE6:34|:393
- 8 - C 04 AND2 0 3 0 5 |CHOICE6:34|:400
- 1 - C 08 OR2 0 3 0 1 |CHOICE6:34|:409
- 8 - C 09 OR2 0 3 0 1 |CHOICE6:34|:412
- 1 - C 06 OR2 0 3 0 1 |CHOICE6:34|:415
- 3 - C 01 OR2 0 3 0 1 |CHOICE6:34|:418
- 4 - C 01 OR2 0 3 0 1 |CHOICE6:34|:421
- 3 - C 10 OR2 0 3 0 1 |CHOICE6:34|:430
- 4 - C 10 OR2 0 3 0 1 |CHOICE6:34|:433
- 5 - C 10 OR2 0 3 0 1 |CHOICE6:34|:436
- 6 - C 10 OR2 0 3 0 1 |CHOICE6:34|:439
- 7 - C 10 OR2 0 3 0 1 |CHOICE6:34|:442
- 3 - C 05 OR2 0 3 0 1 |CHOICE6:34|:451
- 4 - C 05 OR2 0 3 0 1 |CHOICE6:34|:454
- 5 - C 05 OR2 0 3 0 1 |CHOICE6:34|:457
- 7 - C 05 OR2 0 3 0 1 |CHOICE6:34|:460
- 8 - C 05 OR2 0 3 0 1 |CHOICE6:34|:463
- 2 - C 10 OR2 ! 0 4 0 1 |CHOICE6:34|:652
- 4 - C 07 OR2 0 2 0 4 |count24:10|:6
- 3 - C 07 OR2 0 3 0 4 |count24:10|:34
- 7 - C 07 OR2 1 2 0 5 |count24:10|:35
- 5 - C 07 DFFE 0 2 0 4 |count24:10|74161:1|f74161:sub|QA (|count24:10|74161:1|f74161:sub|:9)
- 8 - C 07 DFFE 0 3 0 5 |count24:10|74161:1|f74161:sub|QB (|count24:10|74161:1|f74161:sub|:87)
- 1 - C 07 DFFE 0 4 0 3 |count24:10|74161:1|f74161:sub|QC (|count24:10|74161:1|f74161:sub|:99)
- 2 - C 07 DFFE 0 5 0 3 |count24:10|74161:1|f74161:sub|QD (|count24:10|74161:1|f74161:sub|:110)
- 2 - C 05 DFFE 0 2 0 5 |count24:10|74161:2|f74161:sub|QA (|count24:10|74161:2|f74161:sub|:9)
- 1 - C 05 DFFE 0 3 0 5 |count24:10|74161:2|f74161:sub|QB (|count24:10|74161:2|f74161:sub|:87)
- 8 - C 11 DFFE 0 4 0 3 |count24:10|74161:2|f74161:sub|QC (|count24:10|74161:2|f74161:sub|:99)
- 1 - C 11 DFFE 0 5 0 2 |count24:10|74161:2|f74161:sub|QD (|count24:10|74161:2|f74161:sub|:110)
- 3 - C 08 AND2 ! 0 2 0 4 |count60:11|:6
- 5 - C 08 OR2 1 2 0 4 |count60:11|:31
- 5 - C 09 OR2 1 3 0 4 |count60:11|:32
- 8 - C 08 DFFE + 0 1 0 4 |count60:11|74161:1|f74161:sub|QA (|count60:11|74161:1|f74161:sub|:9)
- 2 - C 08 DFFE + 0 2 0 5 |count60:11|74161:1|f74161:sub|QB (|count60:11|74161:1|f74161:sub|:87)
- 6 - C 08 DFFE + 0 3 0 2 |count60:11|74161:1|f74161:sub|QC (|count60:11|74161:1|f74161:sub|:99)
- 4 - C 08 DFFE + 0 4 0 3 |count60:11|74161:1|f74161:sub|QD (|count60:11|74161:1|f74161:sub|:110)
- 3 - C 09 DFFE 0 2 0 6 |count60:11|74161:2|f74161:sub|QA (|count60:11|74161:2|f74161:sub|:9)
- 4 - C 09 DFFE 0 3 0 5 |count60:11|74161:2|f74161:sub|QB (|count60:11|74161:2|f74161:sub|:87)
- 6 - C 09 DFFE 0 4 0 4 |count60:11|74161:2|f74161:sub|QC (|count60:11|74161:2|f74161:sub|:99)
- 2 - C 09 DFFE 0 5 0 1 |count60:11|74161:2|f74161:sub|QD (|count60:11|74161:2|f74161:sub|:110)
- 6 - C 12 AND2 ! 0 2 0 4 |count60:12|:6
- 6 - C 06 OR2 1 2 0 4 |count60:12|:31
- 5 - C 12 OR2 1 3 0 4 |count60:12|:32
- 4 - C 06 DFFE 0 2 0 5 |count60:12|74161:1|f74161:sub|QA (|count60:12|74161:1|f74161:sub|:9)
- 5 - C 06 DFFE 0 3 0 6 |count60:12|74161:1|f74161:sub|QB (|count60:12|74161:1|f74161:sub|:87)
- 7 - C 06 DFFE 0 4 0 3 |count60:12|74161:1|f74161:sub|QC (|count60:12|74161:1|f74161:sub|:99)
- 3 - C 06 DFFE 0 5 0 4 |count60:12|74161:1|f74161:sub|QD (|count60:12|74161:1|f74161:sub|:110)
- 3 - C 12 DFFE 0 2 0 7 |count60:12|74161:2|f74161:sub|QA (|count60:12|74161:2|f74161:sub|:9)
- 4 - C 12 DFFE 0 3 0 6 |count60:12|74161:2|f74161:sub|QB (|count60:12|74161:2|f74161:sub|:87)
- 1 - C 12 DFFE 0 4 0 5 |count60:12|74161:2|f74161:sub|QC (|count60:12|74161:2|f74161:sub|:99)
- 2 - C 12 DFFE 0 5 0 2 |count60:12|74161:2|f74161:sub|QD (|count60:12|74161:2|f74161:sub|:110)
- 8 - C 06 AND2 s 2 2 0 1 ~35~1
- 2 - C 06 AND2 s 0 4 0 1 ~35~2
- 8 - C 12 AND2 0 4 1 0 :35
- 1 - C 09 OR2 1 3 0 4 :38
- 6 - C 07 OR2 1 3 0 4 :39
- 8 - C 02 OR2 0 2 1 0 :50
- 4 - B 05 OR2 0 4 1 0 |7448:49|OF (|7448:49|:66)
- 1 - B 05 OR2 0 3 1 0 |7448:49|OD (|7448:49|:67)
- 5 - B 05 OR2 0 4 1 0 |7448:49|OB (|7448:49|:68)
- 3 - B 05 OR2 0 4 1 0 |7448:49|OA (|7448:49|:69)
- 7 - B 05 OR2 0 4 1 0 |7448:49|OC (|7448:49|:70)
- 2 - B 05 OR2 0 3 1 0 |7448:49|OE (|7448:49|:71)
- 6 - B 05 OR2 0 4 1 0 |7448:49|OG (|7448:49|:72)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\maxplus_study\tt\eclock\eclock.rpt
eclock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
B: 2/ 96( 2%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 10/ 96( 10%) 32/ 48( 66%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\tt\eclock\eclock.rpt
eclock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 13 clkd
INPUT 5 clk
LCELL 4 |count24:10|:6
LCELL 4 |count60:11|:6
LCELL 4 |count60:12|:6
LCELL 4 :38
LCELL 4 :39
Device-Specific Information: f:\maxplus_study\tt\eclock\eclock.rpt
eclock
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 5 |count24:10|:35
LCELL 4 |count24:10|:34
LCELL 4 |count60:11|:31
LCELL 4 |count60:11|:32
LCELL 4 |count60:12|:31
LCELL 4 |count60:12|:32
Device-Specific Information: f:\maxplus_study\tt\eclock\eclock.rpt
eclock
** EQUATIONS **
clk : INPUT;
clkd : INPUT;
clr : INPUT;
seth : INPUT;
setm : INPUT;
spclk : INPUT;
-- Node name is 'aa'
-- Equation name is 'aa', type is output
aa = _LC3_B5;
-- Node name is 'bb'
-- Equation name is 'bb', type is output
bb = _LC5_B5;
-- Node name is 'cc'
-- Equation name is 'cc', type is output
cc = _LC7_B5;
-- Node name is 'csa'
-- Equation name is 'csa', type is output
csa = _LC1_C4;
-- Node name is 'csb'
-- Equation name is 'csb', type is output
csb = _LC5_C2;
-- Node name is 'csc'
-- Equation name is 'csc', type is output
csc = _LC2_C1;
-- Node name is 'csd'
-- Equation name is 'csd', type is output
csd = _LC3_C2;
-- Node name is 'cse'
-- Equation name is 'cse', type is output
cse = _LC6_C3;
-- Node name is 'csf'
-- Equation name is 'csf', type is output
csf = _LC2_C3;
-- Node name is 'dd'
-- Equation name is 'dd', type is output
dd = _LC1_B5;
-- Node name is 'dop'
-- Equation name is 'dop', type is output
dop = _LC8_C2;
-- Node name is 'ee'
-- Equation name is 'ee', type is output
ee = _LC2_B5;
-- Node name is 'ff'
-- Equation name is 'ff', type is output
ff = _LC4_B5;
-- Node name is 'gg'
-- Equation name is 'gg', type is output
gg = _LC6_B5;
-- Node name is 'speaker'
-- Equation name is 'speaker', type is output
speaker = _LC8_C12;
-- Node name is '|CHOICE6:34|:46' = '|CHOICE6:34|kk0'
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = DFFE( _EQ001, GLOBAL( clkd), VCC, VCC, VCC);
_EQ001 = !_LC8_C4 & _LC8_C5
# _LC2_C5 & _LC8_C4;
-- Node name is '|CHOICE6:34|:45' = '|CHOICE6:34|kk1'
-- Equation name is '_LC1_C10', type is buried
_LC1_C10 = DFFE( _EQ002, GLOBAL( clkd), VCC, VCC, VCC);
_EQ002 = _LC7_C10 & !_LC8_C4
# _LC1_C5 & _LC8_C4;
-- Node name is '|CHOICE6:34|:44' = '|CHOICE6:34|kk2'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = DFFE( _EQ003, GLOBAL( clkd), VCC, VCC, VCC);
_EQ003 = _LC4_C1 & !_LC8_C4
# _LC8_C4 & _LC8_C11;
-- Node name is '|CHOICE6:34|:43' = '|CHOICE6:34|kk3'
-- Equation name is '_LC2_C11', type is buried
_LC2_C11 = DFFE( _EQ004, GLOBAL( clkd), VCC, VCC, VCC);
_EQ004 = _LC7_C11 & !_LC8_C4
# _LC1_C11 & _LC8_C4;
-- Node name is '|CHOICE6:34|:49' = '|CHOICE6:34|qqq0'
-- Equation name is '_LC8_C10', type is buried
_LC8_C10 = DFFE( _EQ005, GLOBAL( clkd), VCC, VCC, VCC);
_EQ005 = !_LC2_C10
# _LC8_C4;
-- Node name is '|CHOICE6:34|:48' = '|CHOICE6:34|qqq1'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = DFFE( _EQ006, GLOBAL( clkd), VCC, VCC, VCC);
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