my_countyb.vhd

来自「大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法」· VHDL 代码 · 共 38 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY my_countyb IS
	PORT(
		cr,cp		: IN	STD_LOGIC;
		qa,qb,qc,qd				: out	STD_LOGIC);
END my_countyb;

ARCHITECTURE a OF my_countyb IS
	SIGNAL qaa,qbb,qcc,qdd: STD_LOGIC;
	SIGNAL nqa,nqb,nqc,nqd: STD_LOGIC;
	SIGNAL kkk: STD_LOGIC;

   component my_d
     port(d,sd,rd		    : IN	STD_LOGIC;
		clk  	    : IN	STD_LOGIC;
		q,nq		: OUT 	STD_LOGIC
	     );
   end component;   
BEGIN
   --nqa<=not qaa;
   --nqb<=not qbb;
   --nqc<=not qcc;
   --nqd<=not qdd;
   kkk<='1';
  U1 : my_d port map (sd => kkk,rd => cr,d => nqa,clk => cp,q => qaa,nq => nqa);
  U2 : my_d port map (sd => kkk,rd => cr,d => nqb,clk => qaa,q => qbb,nq => nqb);
  U3 : my_d port map (sd => kkk,rd => cr,d => nqc,clk => qbb,q => qcc,nq => nqc);
  U4 : my_d port map (sd => kkk,rd => cr,d => nqd,clk => qcc,q => qdd,nq => nqd);
   qa<=qaa;
   qb<=qbb;
   qc<=qcc;
   qd<=qdd;
END a;