📄 my_countyb.rpt
字号:
- 2 - A 14 DFFE + 1 0 0 1 |my_d:U1|ll (|my_d:U1|:9)
- 8 - A 14 AND2 1 1 1 2 |my_d:U1|:107
- 3 - A 14 DFFE 1 2 0 1 |my_d:U2|kk (|my_d:U2|:8)
- 1 - A 14 DFFE 1 1 0 1 |my_d:U2|ll (|my_d:U2|:9)
- 5 - A 14 AND2 1 1 1 2 |my_d:U2|:107
- 6 - A 13 DFFE 1 2 0 1 |my_d:U3|kk (|my_d:U3|:8)
- 4 - A 13 DFFE 1 1 0 1 |my_d:U3|ll (|my_d:U3|:9)
- 3 - A 13 AND2 1 1 1 2 |my_d:U3|:107
- 5 - A 13 DFFE 1 2 0 1 |my_d:U4|kk (|my_d:U4|:8)
- 2 - A 13 DFFE 1 1 0 1 |my_d:U4|ll (|my_d:U4|:9)
- 1 - A 13 AND2 1 1 1 0 |my_d:U4|:107
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\maxplus_study\tt\laji\my_countyb.rpt
my_countyb
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\tt\laji\my_countyb.rpt
my_countyb
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 3 |my_d:U1|:107
LCELL 3 |my_d:U2|:107
LCELL 3 |my_d:U3|:107
INPUT 2 cp
Device-Specific Information: f:\maxplus_study\tt\laji\my_countyb.rpt
my_countyb
** EQUATIONS **
cp : INPUT;
cr : INPUT;
-- Node name is 'qa'
-- Equation name is 'qa', type is output
qa = _LC8_A14;
-- Node name is 'qb'
-- Equation name is 'qb', type is output
qb = _LC5_A14;
-- Node name is 'qc'
-- Equation name is 'qc', type is output
qc = _LC3_A13;
-- Node name is 'qd'
-- Equation name is 'qd', type is output
qd = _LC1_A13;
-- Node name is '|my_d:U1|:8' = '|my_d:U1|kk'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = DFFE( _EQ001, GLOBAL( cp), VCC, VCC, VCC);
_EQ001 = cr & _LC2_A14
# !cr & _LC4_A14;
-- Node name is '|my_d:U1|:9' = '|my_d:U1|ll'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = DFFE( _EQ002, GLOBAL( cp), VCC, VCC, VCC);
_EQ002 = !cr & _LC2_A14
# cr & !_LC2_A14;
-- Node name is '|my_d:U1|:107'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = LCELL( _EQ003);
_EQ003 = cr & _LC4_A14;
-- Node name is '|my_d:U2|:8' = '|my_d:U2|kk'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = DFFE( _EQ004, _LC8_A14, VCC, VCC, VCC);
_EQ004 = cr & _LC1_A14
# !cr & _LC3_A14;
-- Node name is '|my_d:U2|:9' = '|my_d:U2|ll'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = DFFE( _EQ005, _LC8_A14, VCC, VCC, VCC);
_EQ005 = !cr & _LC1_A14
# cr & !_LC1_A14;
-- Node name is '|my_d:U2|:107'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = LCELL( _EQ006);
_EQ006 = cr & _LC3_A14;
-- Node name is '|my_d:U3|:8' = '|my_d:U3|kk'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = DFFE( _EQ007, _LC5_A14, VCC, VCC, VCC);
_EQ007 = cr & _LC4_A13
# !cr & _LC6_A13;
-- Node name is '|my_d:U3|:9' = '|my_d:U3|ll'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = DFFE( _EQ008, _LC5_A14, VCC, VCC, VCC);
_EQ008 = !cr & _LC4_A13
# cr & !_LC4_A13;
-- Node name is '|my_d:U3|:107'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = LCELL( _EQ009);
_EQ009 = cr & _LC6_A13;
-- Node name is '|my_d:U4|:8' = '|my_d:U4|kk'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = DFFE( _EQ010, _LC3_A13, VCC, VCC, VCC);
_EQ010 = cr & _LC2_A13
# !cr & _LC5_A13;
-- Node name is '|my_d:U4|:9' = '|my_d:U4|ll'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = DFFE( _EQ011, _LC3_A13, VCC, VCC, VCC);
_EQ011 = !cr & _LC2_A13
# cr & !_LC2_A13;
-- Node name is '|my_d:U4|:107'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ012);
_EQ012 = cr & _LC5_A13;
Project Information f:\maxplus_study\tt\laji\my_countyb.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,479K
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