📄 my_count8.rpt
字号:
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\tt\my_count8\my_count8.rpt
my_count8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: f:\maxplus_study\tt\my_count8\my_count8.rpt
my_count8
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clr
Device-Specific Information: f:\maxplus_study\tt\my_count8\my_count8.rpt
my_count8
** EQUATIONS **
clk : INPUT;
clr : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
inc : INPUT;
load : INPUT;
-- Node name is ':28' = 'cnt0'
-- Equation name is 'cnt0', location is LC5_C23, type is buried.
cnt0 = DFFE(!cnt0, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d0), !(GLOBAL(!load) & d0), VCC);
-- Node name is ':27' = 'cnt1'
-- Equation name is 'cnt1', location is LC6_C24, type is buried.
cnt1 = DFFE( _EQ001, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d1), !(GLOBAL(!load) & d1), VCC);
_EQ001 = _LC1_C24 & _LC6_C16
# _LC4_C24;
-- Node name is ':26' = 'cnt2'
-- Equation name is 'cnt2', location is LC2_C24, type is buried.
cnt2 = DFFE( _EQ002, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d2), !(GLOBAL(!load) & d2), VCC);
_EQ002 = !inc & _LC5_C24
# _LC8_C24;
-- Node name is ':25' = 'cnt3'
-- Equation name is 'cnt3', location is LC1_C23, type is buried.
cnt3 = DFFE( _EQ003, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d3), !(GLOBAL(!load) & d3), VCC);
_EQ003 = _LC3_C23
# _LC4_C23 & _LC6_C16;
-- Node name is ':24' = 'cnt4'
-- Equation name is 'cnt4', location is LC1_C18, type is buried.
cnt4 = DFFE( _EQ004, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d4), !(GLOBAL(!load) & d4), VCC);
_EQ004 = _LC2_C18
# !inc & _LC3_C18;
-- Node name is ':23' = 'cnt5'
-- Equation name is 'cnt5', location is LC6_C18, type is buried.
cnt5 = DFFE( _EQ005, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d5), !(GLOBAL(!load) & d5), VCC);
_EQ005 = !inc & _LC7_C18
# _LC8_C18;
-- Node name is ':22' = 'cnt6'
-- Equation name is 'cnt6', location is LC1_C16, type is buried.
cnt6 = DFFE( _EQ006, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d6), !(GLOBAL(!load) & d6), VCC);
_EQ006 = !inc & _LC3_C16
# _LC5_C16;
-- Node name is ':21' = 'cnt7'
-- Equation name is 'cnt7', location is LC4_C16, type is buried.
cnt7 = DFFE( _EQ007, GLOBAL(!clk), GLOBAL( clr) & !(GLOBAL(!load) & !d7), !(GLOBAL(!load) & d7), VCC);
_EQ007 = _LC7_C16
# !inc & _LC8_C16;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = cnt0;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = cnt1;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = cnt2;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = cnt3;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = cnt4;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = cnt5;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = cnt6;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = cnt7;
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C24', type is buried
!_LC7_C24 = _LC7_C24~NOT;
_LC7_C24~NOT = LCELL( _EQ008);
_EQ008 = !cnt3
# !cnt2
# !cnt1
# !cnt0;
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C18', type is buried
!_LC5_C18 = _LC5_C18~NOT;
_LC5_C18~NOT = LCELL( _EQ009);
_EQ009 = !cnt5
# !cnt4
# !_LC7_C24;
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|:107' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = LCELL( _EQ010);
_EQ010 = !cnt0 & cnt1
# cnt0 & !cnt1;
-- Node name is '|LPM_ADD_SUB:95|addcore:adder|:109' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = LCELL( _EQ011);
_EQ011 = !cnt1 & cnt3
# !cnt0 & cnt3
# !cnt2 & cnt3
# cnt0 & cnt1 & cnt2 & !cnt3;
-- Node name is '|LPM_ADD_SUB:193|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ012);
_EQ012 = cnt1
# cnt0
# cnt2;
-- Node name is '|LPM_ADD_SUB:193|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C24', type is buried
!_LC3_C24 = _LC3_C24~NOT;
_LC3_C24~NOT = LCELL( _EQ013);
_EQ013 = !cnt0 & !cnt1 & !cnt2 & !cnt3;
-- Node name is '|LPM_ADD_SUB:193|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_C18', type is buried
!_LC4_C18 = _LC4_C18~NOT;
_LC4_C18~NOT = LCELL( _EQ014);
_EQ014 = !cnt4 & !cnt5 & !_LC3_C24;
-- Node name is ':167'
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = LCELL( _EQ015);
_EQ015 = !cnt6 & !cnt7 & !_LC4_C18;
-- Node name is ':211'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = LCELL( _EQ016);
_EQ016 = cnt6 & cnt7
# cnt7 & _LC4_C18
# !cnt6 & !cnt7 & !_LC4_C18;
-- Node name is ':217'
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = LCELL( _EQ017);
_EQ017 = cnt6 & _LC4_C18
# !cnt6 & !_LC4_C18;
-- Node name is ':223'
-- Equation name is '_LC7_C18', type is buried
_LC7_C18 = LCELL( _EQ018);
_EQ018 = cnt4 & cnt5
# cnt5 & _LC3_C24
# !cnt4 & !cnt5 & !_LC3_C24
# _LC2_C16;
-- Node name is ':229'
-- Equation name is '_LC3_C18', type is buried
_LC3_C18 = LCELL( _EQ019);
_EQ019 = cnt4 & _LC3_C24
# !cnt4 & !_LC3_C24
# _LC2_C16;
-- Node name is ':241'
-- Equation name is '_LC5_C24', type is buried
_LC5_C24 = LCELL( _EQ020);
_EQ020 = cnt1 & cnt2
# cnt0 & cnt2
# !cnt0 & !cnt1 & !cnt2
# _LC2_C16;
-- Node name is ':266'
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = LCELL( _EQ021);
_EQ021 = cnt6 & !cnt7 & inc & _LC5_C18
# !cnt6 & cnt7 & inc
# cnt7 & inc & !_LC5_C18;
-- Node name is ':272'
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = LCELL( _EQ022);
_EQ022 = cnt6 & inc & !_LC5_C18
# !cnt6 & inc & _LC5_C18;
-- Node name is ':278'
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = LCELL( _EQ023);
_EQ023 = !cnt4 & cnt5 & _LC6_C16
# cnt5 & _LC6_C16 & !_LC7_C24
# cnt4 & !cnt5 & _LC6_C16 & _LC7_C24;
-- Node name is ':284'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = LCELL( _EQ024);
_EQ024 = cnt4 & _LC6_C16 & !_LC7_C24
# !cnt4 & _LC6_C16 & _LC7_C24;
-- Node name is ':291'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = LCELL( _EQ025);
_EQ025 = cnt3 & !inc & _LC2_C23
# !cnt3 & !inc & !_LC2_C23
# !inc & _LC2_C16;
-- Node name is ':296'
-- Equation name is '_LC8_C24', type is buried
_LC8_C24 = LCELL( _EQ026);
_EQ026 = !cnt1 & cnt2 & _LC6_C16
# !cnt0 & cnt2 & _LC6_C16
# cnt0 & cnt1 & !cnt2 & _LC6_C16;
-- Node name is '~302~1'
-- Equation name is '~302~1', location is LC6_C16, type is buried.
-- synthesized logic cell
_LC6_C16 = LCELL( _EQ027);
_EQ027 = !cnt7 & inc
# !cnt6 & inc
# inc & !_LC5_C18;
-- Node name is ':303'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = LCELL( _EQ028);
_EQ028 = !inc & _LC2_C16
# cnt0 & cnt1 & !inc
# !cnt0 & !cnt1 & !inc;
Project Information f:\maxplus_study\tt\my_count8\my_count8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,397K
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