my_count8.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II VHDL
-- Clearable my_count8

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY my_count8 IS
	PORT(inc,load,clk,clr		    : IN	STD_LOGIC;
		 d				            : IN	integer range 0 to 255;
		 q				            : out	integer range 0 to 255);
END my_count8;

ARCHITECTURE aaa OF my_count8 IS
BEGIN
    P2:process(clk,clr,load)
       variable cnt : integer range 0 to 255;
     begin 
       if(clk='0'and clk'event)then 
                       if(inc='1') then 
                                     if(cnt=255)then cnt:=0;
                                     else cnt:=cnt+1;
                                     end if;
                       else 
                                     if(cnt=0)then cnt:=255;
                                     else cnt:=cnt-1;
                                     end if;
                       end if;
       end if;
       if(clr='0')then cnt:=0;
        end if;
        if(load='0')then cnt:=d;
        end if;
        q<=cnt;
    end process;
END aaa;