clockcontroll.rpt

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
21:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
22:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:f:\maxplus_study\maxshiyan\traffic\clockcontroll.rpt
clockcontroll

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       13         co


Device-Specific Information:f:\maxplus_study\maxshiyan\traffic\clockcontroll.rpt
clockcontroll

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT       13         res


Device-Specific Information:f:\maxplus_study\maxshiyan\traffic\clockcontroll.rpt
clockcontroll

** EQUATIONS **

co       : INPUT;
res      : INPUT;

-- Node name is 'ewgreen' 
-- Equation name is 'ewgreen', type is output 
ewgreen  =  _LC3_A20;

-- Node name is 'ewred' 
-- Equation name is 'ewred', type is output 
ewred    =  _LC7_A20;

-- Node name is 'ewyellow' 
-- Equation name is 'ewyellow', type is output 
ewyellow =  _LC7_A21;

-- Node name is 'q0' 
-- Equation name is 'q0', type is output 
q0       =  _LC4_A20;

-- Node name is 'q1' 
-- Equation name is 'q1', type is output 
q1       =  _LC1_A21;

-- Node name is 'q2' 
-- Equation name is 'q2', type is output 
q2       =  _LC5_A21;

-- Node name is 'q3' 
-- Equation name is 'q3', type is output 
q3       =  _LC5_A20;

-- Node name is 'sngreen' 
-- Equation name is 'sngreen', type is output 
sngreen  =  _LC1_A20;

-- Node name is 'snred' 
-- Equation name is 'snred', type is output 
snred    =  _LC8_A20;

-- Node name is 'snyellow' 
-- Equation name is 'snyellow', type is output 
snyellow =  _LC2_A20;

-- Node name is 'spark' 
-- Equation name is 'spark', type is output 
spark    =  _LC2_A21;

-- Node name is ':28' = 'state0' 
-- Equation name is 'state0', location is LC8_A21, type is buried.
state0   = DFFE(!state0, GLOBAL( co), GLOBAL( res),  VCC,  VCC);

-- Node name is ':27' = 'state1' 
-- Equation name is 'state1', location is LC4_A21, type is buried.
state1   = DFFE( _EQ001, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ001 = !state0 &  state1
         #  state0 & !state1;

-- Node name is ':3' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = DFFE( _EQ002, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ002 = !_LC3_A21 &  _LC5_A20 &  _LC6_A20 & !_LC6_A21;

-- Node name is ':5' 
-- Equation name is '_LC5_A21', type is buried 
!_LC5_A21 = _LC5_A21~NOT;
_LC5_A21~NOT = DFFE(!state0, GLOBAL( co), GLOBAL( res),  VCC,  VCC);

-- Node name is ':7' 
-- Equation name is '_LC1_A21', type is buried 
_LC1_A21 = DFFE(!state0, GLOBAL( co), GLOBAL( res),  VCC,  VCC);

-- Node name is ':9' 
-- Equation name is '_LC4_A20', type is buried 
!_LC4_A20 = _LC4_A20~NOT;
_LC4_A20~NOT = DFFE( _EQ003, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ003 = !_LC3_A21 & !_LC4_A20 &  _LC6_A20 & !_LC6_A21;

-- Node name is ':11' 
-- Equation name is '_LC3_A20', type is buried 
!_LC3_A20 = _LC3_A20~NOT;
_LC3_A20~NOT = DFFE( _EQ004, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ004 = !_LC3_A20 &  _LC6_A20
         #  _LC6_A20 &  _LC6_A21
         #  _LC3_A21 &  _LC6_A20;

-- Node name is ':13' 
-- Equation name is '_LC7_A21', type is buried 
_LC7_A21 = DFFE( _EQ005, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ005 = !state0 & !state1;

-- Node name is ':15' 
-- Equation name is '_LC7_A20', type is buried 
_LC7_A20 = DFFE( _EQ006, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ006 =  _LC6_A20 &  _LC7_A20
         #  _LC6_A20 &  _LC6_A21
         #  _LC3_A21 &  _LC6_A20;

-- Node name is ':17' 
-- Equation name is '_LC1_A20', type is buried 
_LC1_A20 = DFFE( _EQ007, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ007 =  _LC1_A20 &  _LC6_A20
         #  _LC6_A20 &  _LC6_A21
         #  _LC3_A21 &  _LC6_A20;

-- Node name is ':19' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = DFFE( _EQ008, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ008 =  _LC2_A20 &  _LC6_A20 & !_LC6_A21
         #  _LC3_A21 &  _LC6_A20 & !_LC6_A21;

-- Node name is ':21' 
-- Equation name is '_LC8_A20', type is buried 
!_LC8_A20 = _LC8_A20~NOT;
_LC8_A20~NOT = DFFE( _EQ009, GLOBAL( co), GLOBAL( res),  VCC,  VCC);
  _EQ009 =  _LC6_A20 & !_LC8_A20
         #  _LC6_A20 &  _LC6_A21
         #  _LC3_A21 &  _LC6_A20;

-- Node name is ':23' 
-- Equation name is '_LC2_A21', type is buried 
_LC2_A21 = DFFE(!state0, GLOBAL( co), GLOBAL( res),  VCC,  VCC);

-- Node name is ':181' 
-- Equation name is '_LC6_A21', type is buried 
_LC6_A21 = LCELL( _EQ010);
  _EQ010 =  state0 & !state1;

-- Node name is ':184' 
-- Equation name is '_LC3_A21', type is buried 
_LC3_A21 = LCELL( _EQ011);
  _EQ011 = !state0 &  state1;

-- Node name is '~364~1' 
-- Equation name is '~364~1', location is LC6_A20, type is buried.
-- synthesized logic cell 
_LC6_A20 = LCELL( _EQ012);
  _EQ012 = !state0 &  state1
         #  state0 & !state1;



Project Information       f:\maxplus_study\maxshiyan\traffic\clockcontroll.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,229K