📄 traffic.rpt
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# _LC1_B16 & _LC4_B16;
-- Node name is '|CLOCKCONTROLL:32|:19'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = DFFE( _EQ008, _LC2_B20, res, VCC, VCC);
_EQ008 = !_LC3_B16 & _LC4_B16 & _LC5_B14
# _LC1_B16 & !_LC3_B16 & _LC4_B16;
-- Node name is '|CLOCKCONTROLL:32|:21'
-- Equation name is '_LC8_B14', type is buried
!_LC8_B14 = _LC8_B14~NOT;
_LC8_B14~NOT = DFFE( _EQ009, _LC2_B20, res, VCC, VCC);
_EQ009 = _LC4_B16 & !_LC8_B14
# _LC3_B16 & _LC4_B16
# _LC1_B16 & _LC4_B16;
-- Node name is '|CLOCKCONTROLL:32|:23'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = DFFE(!_LC3_B14, _LC2_B20, res, VCC, VCC);
-- Node name is '|CLOCKCONTROLL:32|:181'
-- Equation name is '_LC3_B16', type is buried
!_LC3_B16 = _LC3_B16~NOT;
_LC3_B16~NOT = LCELL( _EQ010);
_EQ010 = _LC5_B16
# !_LC3_B14;
-- Node name is '|CLOCKCONTROLL:32|:184'
-- Equation name is '_LC1_B16', type is buried
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL( _EQ011);
_EQ011 = _LC3_B14
# !_LC5_B16;
-- Node name is '|CLOCKCONTROLL:32|~364~1'
-- Equation name is '_LC4_B16', type is buried
-- synthesized logic cell
_LC4_B16 = LCELL( _EQ012);
_EQ012 = !_LC3_B14 & _LC5_B16
# _LC3_B14 & !_LC5_B16;
-- Node name is '|my_count3_5:33|:14' = '|my_count3_5:33|co'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ013);
_EQ013 = !_LC1_B20 & !_LC2_B24 & !_LC7_B9 & !_LC8_B16;
-- Node name is '|my_count3_5:33|:23'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = LCELL( _EQ014);
_EQ014 = _LC2_B24 & res
# _LC7_B9 & res
# _LC4_B20 & res;
-- Node name is '|my_count3_5:33|74193:1|:26' = '|my_count3_5:33|74193:1|QA'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = DFFE(!_LC2_B24, GLOBAL( clk), !(!_LC3_B20 & _LC8_B24), !(!_LC3_B20 & !_LC8_B24), VCC);
-- Node name is '|my_count3_5:33|74193:1|:25' = '|my_count3_5:33|74193:1|QB'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = DFFE(!_LC8_B16, !_LC7_B16, !(!_LC3_B20 & !_LC6_B16), !(!_LC3_B20 & _LC6_B16), VCC);
-- Node name is '|my_count3_5:33|74193:1|:24' = '|my_count3_5:33|74193:1|QC'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = DFFE(!_LC1_B20, !_LC8_B20, !(!_LC3_B20 & _LC6_B20), !(!_LC3_B20 & !_LC6_B20), VCC);
-- Node name is '|my_count3_5:33|74193:1|:23' = '|my_count3_5:33|74193:1|QD'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = DFFE(!_LC7_B9, !_LC8_B9, !(!_LC3_B20 & !_LC1_B14), !(!_LC3_B20 & _LC1_B14), VCC);
-- Node name is '|my_count3_5:33|74193:1|:6'
-- Equation name is '_LC7_B16', type is buried
!_LC7_B16 = _LC7_B16~NOT;
_LC7_B16~NOT = LCELL( _EQ015);
_EQ015 = _LC2_B24
# clk;
-- Node name is '|my_count3_5:33|74193:1|:22'
-- Equation name is '_LC8_B9', type is buried
!_LC8_B9 = _LC8_B9~NOT;
_LC8_B9~NOT = LCELL( _EQ016);
_EQ016 = _LC2_B24
# clk
# _LC8_B16
# _LC1_B20;
-- Node name is '|my_count3_5:33|74193:1|:50'
-- Equation name is '_LC8_B20', type is buried
!_LC8_B20 = _LC8_B20~NOT;
_LC8_B20~NOT = LCELL( _EQ017);
_EQ017 = _LC8_B16
# _LC2_B24
# clk;
-- Node name is '|7448:31|:69' = '|7448:31|OA'
-- Equation name is '_LC3_B9', type is buried
_LC3_B9 = LCELL( _EQ018);
_EQ018 = _LC2_B24 & !_LC7_B9 & _LC8_B16
# _LC1_B20 & _LC2_B24 & !_LC7_B9
# !_LC1_B20 & !_LC7_B9 & _LC8_B16
# !_LC1_B20 & !_LC2_B24 & !_LC7_B9
# _LC1_B20 & _LC2_B24 & !_LC8_B16
# _LC2_B24 & _LC7_B9 & !_LC8_B16
# !_LC1_B20 & !_LC2_B24 & !_LC8_B16
# !_LC1_B20 & _LC7_B9 & !_LC8_B16;
-- Node name is '|7448:31|:68' = '|7448:31|OB'
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ019);
_EQ019 = !_LC2_B24 & !_LC8_B16
# _LC2_B24 & !_LC7_B9 & _LC8_B16
# !_LC1_B20 & !_LC7_B9
# !_LC1_B20 & !_LC8_B16;
-- Node name is '|7448:31|:70' = '|7448:31|OC'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = LCELL( _EQ020);
_EQ020 = _LC2_B24 & !_LC7_B9
# !_LC1_B20 & _LC2_B24
# !_LC7_B9 & !_LC8_B16
# !_LC1_B20 & !_LC8_B16
# _LC1_B20 & !_LC7_B9;
-- Node name is '|7448:31|:67' = '|7448:31|OD'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ021);
_EQ021 = !_LC2_B24 & _LC8_B16
# _LC1_B20 & _LC2_B24 & !_LC8_B16
# !_LC1_B20 & _LC8_B16
# !_LC1_B20 & !_LC2_B24;
-- Node name is '|7448:31|:71' = '|7448:31|OE'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ022);
_EQ022 = !_LC2_B24 & _LC8_B16
# !_LC1_B20 & !_LC2_B24;
-- Node name is '|7448:31|:66' = '|7448:31|OF'
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = LCELL( _EQ023);
_EQ023 = !_LC2_B24 & !_LC8_B16
# _LC7_B9 & !_LC8_B16
# _LC1_B20 & !_LC2_B24
# _LC1_B20 & !_LC8_B16;
-- Node name is '|7448:31|:72' = '|7448:31|OG'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = LCELL( _EQ024);
_EQ024 = !_LC2_B24 & _LC8_B16
# _LC1_B20 & !_LC2_B24
# !_LC2_B24 & _LC7_B9
# _LC1_B20 & !_LC8_B16
# _LC7_B9 & !_LC8_B16
# !_LC1_B20 & _LC8_B16
# !_LC1_B20 & _LC7_B9;
-- Node name is '|7448:31|~38~1'
-- Equation name is '_LC4_B20', type is buried
-- synthesized logic cell
_LC4_B20 = LCELL( _EQ025);
_EQ025 = _LC8_B16
# _LC1_B20;
-- Node name is ':27'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ026);
_EQ026 = _LC4_B24 & !_LC6_B14
# clk & _LC4_B24;
-- Node name is ':28'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ027);
_EQ027 = !_LC6_B14 & _LC7_B24
# clk & _LC7_B24;
Project Information f:\maxplus_study\maxshiyan\traffic\traffic.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,415K
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