📄 traffic.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\maxplus_study\maxshiyan\traffic\traffic.rpt
traffic
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 14 DFFE 1 4 0 1 |CLOCKCONTROLL:32|:3
- 6 - B 20 SOFT s ! 0 1 0 1 |CLOCKCONTROLL:32|~5~1
- 5 - B 20 DFFE ! 1 2 0 1 |CLOCKCONTROLL:32|:5
- 6 - B 16 DFFE 1 2 0 1 |CLOCKCONTROLL:32|:7
- 8 - B 24 SOFT s ! 0 1 0 1 |CLOCKCONTROLL:32|~9~1
- 3 - B 24 DFFE ! 1 4 0 1 |CLOCKCONTROLL:32|:9
- 4 - B 24 DFFE ! 1 4 0 1 |CLOCKCONTROLL:32|:11
- 2 - B 16 DFFE 1 3 1 0 |CLOCKCONTROLL:32|:13
- 1 - B 24 DFFE 1 4 1 0 |CLOCKCONTROLL:32|:15
- 7 - B 24 DFFE 1 4 0 1 |CLOCKCONTROLL:32|:17
- 5 - B 14 DFFE 1 4 1 0 |CLOCKCONTROLL:32|:19
- 8 - B 14 DFFE ! 1 4 1 0 |CLOCKCONTROLL:32|:21
- 6 - B 14 DFFE 1 2 0 2 |CLOCKCONTROLL:32|:23
- 5 - B 16 DFFE 1 2 0 4 |CLOCKCONTROLL:32|state1 (|CLOCKCONTROLL:32|:27)
- 3 - B 14 DFFE 1 1 0 8 |CLOCKCONTROLL:32|state0 (|CLOCKCONTROLL:32|:28)
- 3 - B 16 OR2 ! 0 2 0 7 |CLOCKCONTROLL:32|:181
- 1 - B 16 OR2 ! 0 2 0 7 |CLOCKCONTROLL:32|:184
- 4 - B 16 OR2 s 0 2 0 7 |CLOCKCONTROLL:32|~364~1
- 2 - B 20 AND2 0 4 0 13 |my_count3_5:33|co (|my_count3_5:33|:14)
- 3 - B 20 OR2 1 3 0 4 |my_count3_5:33|:23
- 7 - B 16 OR2 ! 1 1 0 1 |my_count3_5:33|74193:1|:6
- 8 - B 09 OR2 ! 1 3 0 1 |my_count3_5:33|74193:1|:22
- 7 - B 09 DFFE 0 3 0 7 |my_count3_5:33|74193:1|QD (|my_count3_5:33|74193:1|:23)
- 1 - B 20 DFFE 0 3 0 10 |my_count3_5:33|74193:1|QC (|my_count3_5:33|74193:1|:24)
- 8 - B 16 DFFE 0 3 0 11 |my_count3_5:33|74193:1|QB (|my_count3_5:33|74193:1|:25)
- 2 - B 24 DFFE + 0 2 0 12 |my_count3_5:33|74193:1|QA (|my_count3_5:33|74193:1|:26)
- 8 - B 20 OR2 ! 1 2 0 1 |my_count3_5:33|74193:1|:50
- 5 - B 24 OR2 1 2 1 0 :27
- 6 - B 24 OR2 1 2 1 0 :28
- 4 - B 20 OR2 s 0 2 0 1 |7448:31|~38~1
- 4 - B 09 OR2 0 4 1 0 |7448:31|OF (|7448:31|:66)
- 1 - B 09 OR2 0 3 1 0 |7448:31|OD (|7448:31|:67)
- 5 - B 09 OR2 0 4 1 0 |7448:31|OB (|7448:31|:68)
- 3 - B 09 OR2 0 4 1 0 |7448:31|OA (|7448:31|:69)
- 7 - B 20 OR2 0 4 1 0 |7448:31|OC (|7448:31|:70)
- 2 - B 09 OR2 0 3 1 0 |7448:31|OE (|7448:31|:71)
- 6 - B 09 OR2 0 4 1 0 |7448:31|OG (|7448:31|:72)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\maxplus_study\maxshiyan\traffic\traffic.rpt
traffic
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 8/ 96( 8%) 4/ 48( 8%) 13/ 48( 27%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\maxplus_study\maxshiyan\traffic\traffic.rpt
traffic
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 13 |my_count3_5:33|co
INPUT 6 clk
LCELL 1 |my_count3_5:33|74193:1|:6
LCELL 1 |my_count3_5:33|74193:1|:22
LCELL 1 |my_count3_5:33|74193:1|:50
Device-Specific Information: f:\maxplus_study\maxshiyan\traffic\traffic.rpt
traffic
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 14 res
Device-Specific Information: f:\maxplus_study\maxshiyan\traffic\traffic.rpt
traffic
** EQUATIONS **
clk : INPUT;
res : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC3_B9;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC5_B9;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC7_B20;
-- Node name is 'cs'
-- Equation name is 'cs', type is output
cs = VCC;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC1_B9;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC2_B9;
-- Node name is 'eg'
-- Equation name is 'eg', type is output
eg = _LC5_B24;
-- Node name is 'er'
-- Equation name is 'er', type is output
er = _LC1_B24;
-- Node name is 'ey'
-- Equation name is 'ey', type is output
ey = _LC2_B16;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC4_B9;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC6_B9;
-- Node name is 'sg'
-- Equation name is 'sg', type is output
sg = _LC6_B24;
-- Node name is 'sr'
-- Equation name is 'sr', type is output
sr = _LC8_B14;
-- Node name is 'sy'
-- Equation name is 'sy', type is output
sy = _LC5_B14;
-- Node name is '|CLOCKCONTROLL:32|:28' = '|CLOCKCONTROLL:32|state0'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = DFFE(!_LC3_B14, _LC2_B20, res, VCC, VCC);
-- Node name is '|CLOCKCONTROLL:32|:27' = '|CLOCKCONTROLL:32|state1'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = DFFE( _EQ001, _LC2_B20, res, VCC, VCC);
_EQ001 = !_LC3_B14 & _LC5_B16
# _LC3_B14 & !_LC5_B16;
-- Node name is '|CLOCKCONTROLL:32|:3'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = DFFE( _EQ002, _LC2_B20, res, VCC, VCC);
_EQ002 = _LC1_B14 & !_LC1_B16 & !_LC3_B16 & _LC4_B16;
-- Node name is '|CLOCKCONTROLL:32|~5~1'
-- Equation name is '_LC6_B20', type is buried
-- synthesized logic cell
!_LC6_B20 = _LC6_B20~NOT;
_LC6_B20~NOT = LCELL( _LC5_B20);
-- Node name is '|CLOCKCONTROLL:32|:5'
-- Equation name is '_LC5_B20', type is buried
!_LC5_B20 = _LC5_B20~NOT;
_LC5_B20~NOT = DFFE(!_LC3_B14, _LC2_B20, res, VCC, VCC);
-- Node name is '|CLOCKCONTROLL:32|:7'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = DFFE(!_LC3_B14, _LC2_B20, res, VCC, VCC);
-- Node name is '|CLOCKCONTROLL:32|~9~1'
-- Equation name is '_LC8_B24', type is buried
-- synthesized logic cell
!_LC8_B24 = _LC8_B24~NOT;
_LC8_B24~NOT = LCELL( _LC3_B24);
-- Node name is '|CLOCKCONTROLL:32|:9'
-- Equation name is '_LC3_B24', type is buried
!_LC3_B24 = _LC3_B24~NOT;
_LC3_B24~NOT = DFFE( _EQ003, _LC2_B20, res, VCC, VCC);
_EQ003 = !_LC1_B16 & !_LC3_B16 & !_LC3_B24 & _LC4_B16;
-- Node name is '|CLOCKCONTROLL:32|:11'
-- Equation name is '_LC4_B24', type is buried
!_LC4_B24 = _LC4_B24~NOT;
_LC4_B24~NOT = DFFE( _EQ004, _LC2_B20, res, VCC, VCC);
_EQ004 = _LC4_B16 & !_LC4_B24
# _LC3_B16 & _LC4_B16
# _LC1_B16 & _LC4_B16;
-- Node name is '|CLOCKCONTROLL:32|:13'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = DFFE( _EQ005, _LC2_B20, res, VCC, VCC);
_EQ005 = !_LC3_B14 & !_LC5_B16;
-- Node name is '|CLOCKCONTROLL:32|:15'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = DFFE( _EQ006, _LC2_B20, res, VCC, VCC);
_EQ006 = _LC1_B24 & _LC4_B16
# _LC3_B16 & _LC4_B16
# _LC1_B16 & _LC4_B16;
-- Node name is '|CLOCKCONTROLL:32|:17'
-- Equation name is '_LC7_B24', type is buried
_LC7_B24 = DFFE( _EQ007, _LC2_B20, res, VCC, VCC);
_EQ007 = _LC4_B16 & _LC7_B24
# _LC3_B16 & _LC4_B16
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