📄 my_count3_5.rpt
字号:
- 2 - C 22 AND2 1 1 0 4 :23
- 3 - C 22 OR2 ! 1 1 0 1 |74193:1|:6
- 1 - C 22 OR2 ! 1 3 0 1 |74193:1|:22
- 2 - C 16 DFFE 1 2 1 1 |74193:1|QD (|74193:1|:23)
- 5 - C 22 DFFE 1 2 1 2 |74193:1|QC (|74193:1|:24)
- 4 - C 22 DFFE 1 2 1 3 |74193:1|QB (|74193:1|:25)
- 1 - C 16 DFFE + 1 1 1 4 |74193:1|QA (|74193:1|:26)
- 6 - C 22 OR2 ! 1 2 0 1 |74193:1|:50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:f:\maxplus_study\maxshiyan\traffic\my_count3_5.rpt
my_count3_5
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:f:\maxplus_study\maxshiyan\traffic\my_count3_5.rpt
my_count3_5
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
LCELL 1 |74193:1|:6
LCELL 1 |74193:1|:22
LCELL 1 |74193:1|:50
Device-Specific Information:f:\maxplus_study\maxshiyan\traffic\my_count3_5.rpt
my_count3_5
** EQUATIONS **
a : INPUT;
b : INPUT;
c : INPUT;
clk : INPUT;
d : INPUT;
ld : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC7_C22;
-- Node name is 'qa'
-- Equation name is 'qa', type is output
qa = _LC1_C16;
-- Node name is 'qb'
-- Equation name is 'qb', type is output
qb = _LC4_C22;
-- Node name is 'qc'
-- Equation name is 'qc', type is output
qc = _LC5_C22;
-- Node name is 'qd'
-- Equation name is 'qd', type is output
qd = _LC2_C16;
-- Node name is '|74193:1|:26' = '|74193:1|QA'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = DFFE(!_LC1_C16, GLOBAL( clk), !(!_LC2_C22 & !a), !(!_LC2_C22 & a), VCC);
-- Node name is '|74193:1|:25' = '|74193:1|QB'
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = DFFE(!_LC4_C22, !_LC3_C22, !(!_LC2_C22 & !b), !(!_LC2_C22 & b), VCC);
-- Node name is '|74193:1|:24' = '|74193:1|QC'
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = DFFE(!_LC5_C22, !_LC6_C22, !(!_LC2_C22 & !c), !(!_LC2_C22 & c), VCC);
-- Node name is '|74193:1|:23' = '|74193:1|QD'
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = DFFE(!_LC2_C16, !_LC1_C22, !(!_LC2_C22 & !d), !(!_LC2_C22 & d), VCC);
-- Node name is '|74193:1|:6'
-- Equation name is '_LC3_C22', type is buried
!_LC3_C22 = _LC3_C22~NOT;
_LC3_C22~NOT = LCELL( _EQ001);
_EQ001 = _LC1_C16
# clk;
-- Node name is '|74193:1|:22'
-- Equation name is '_LC1_C22', type is buried
!_LC1_C22 = _LC1_C22~NOT;
_LC1_C22~NOT = LCELL( _EQ002);
_EQ002 = _LC1_C16
# clk
# _LC4_C22
# _LC5_C22;
-- Node name is '|74193:1|:50'
-- Equation name is '_LC6_C22', type is buried
!_LC6_C22 = _LC6_C22~NOT;
_LC6_C22~NOT = LCELL( _EQ003);
_EQ003 = _LC1_C16
# clk
# _LC4_C22;
-- Node name is ':14'
-- Equation name is '_LC7_C22', type is buried
!_LC7_C22 = _LC7_C22~NOT;
_LC7_C22~NOT = LCELL( _EQ004);
_EQ004 = _LC2_C16
# _LC5_C22
# _LC1_C16
# _LC4_C22;
-- Node name is ':23'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = LCELL( _EQ005);
_EQ005 = !_LC7_C22 & ld;
Project Information f:\maxplus_study\maxshiyan\traffic\my_count3_5.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,626K
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