clockcontroll.vhd

大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟

-- MAX+plus II VHDL
-- Clearable clockcontroll

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY clockcontroll IS
	PORT(co,res               : IN	STD_LOGIC;
         q				: out	STD_LOGIC_VECTOR(3 downto 0);
         ewgreen,ewyellow,ewred,sngreen,snyellow,snred		            : out	STD_LOGIC;
		 spark				            : out	STD_LOGIC);
END clockcontroll;

ARCHITECTURE aaa OF clockcontroll IS
BEGIN
   P1:process(co,res)
     variable state : integer range 0 to 3;
    begin 
     if(res='0')then state:=0;ewgreen<='1';ewyellow<='0';ewred<='0';sngreen<='0';snyellow<='0';snred<='1';
                    q<="0101";spark<='0';
     elsif(co='1' and co'event )then 
             if(state=0)then state:=1;
             elsif(state=1)then state:=2;
             elsif(state=2)then state:=3;
             elsif(state=3)then state:=0;
             end if;
             if(state=0)then ewgreen<='1';ewyellow<='0';ewred<='0';sngreen<='0';snyellow<='0';snred<='1';
                    q<="0101";spark<='0';
             elsif(state=1)then ewgreen<='1';ewyellow<='1';ewred<='0';sngreen<='0';snyellow<='0';snred<='1';
                    q<="0011";spark<='1';
             elsif(state=2)then ewgreen<='0';ewyellow<='0';ewred<='1';sngreen<='1';snyellow<='0';snred<='0';
                    q<="0101";spark<='0';
             elsif(state=3)then ewgreen<='0';ewyellow<='0';ewred<='1';sngreen<='1';snyellow<='1';snred<='0';
                    q<="0011";spark<='1';
             end if;
        else NULL;
        end if;
      end process;
 END aaa;