z_test.vhd

来自「数据选择器」· VHDL 代码 · 共 53 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Z_TEST IS
	PORT(A1:IN STD_LOGIC;
		B1:IN STD_LOGIC;
		O1:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

		A2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		C2:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		O2:OUT STD_LOGIC;

		A3:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		O3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
END ENTITY Z_TEST;

ARCHITECTURE ART OF Z_TEST IS
BEGIN

PROCESS (A1,B1) IS
BEGIN
O1(0)<=A1 XOR B1;
O1(1)<=A1 AND B1;
END PROCESS;

PROCESS (A2,C2) IS 
BEGIN
CASE C2 IS
	WHEN "00"=>O2<=A2(0);
	WHEN "01"=>O2<=A2(1);
	WHEN "10"=>O2<=A2(2);
	WHEN "11"=>O2<=A2(3);
	WHEN OTHERS =>O2<='X';
END CASE;
END PROCESS;

PROCESS (A3) IS 
BEGIN
CASE A3 IS
	WHEN "000"=>O3<="00000001";
	WHEN "001"=>O3<="00000010";
	WHEN "010"=>O3<="00000100";
	WHEN "011"=>O3<="00001000";
	WHEN "100"=>O3<="00010000";
	WHEN "101"=>O3<="00100000";
	WHEN "110"=>O3<="01000000";
	WHEN "111"=>O3<="10000000";
	WHEN OTHERS =>O3<="XXXXXXXX";
END CASE;
END PROCESS;

END ARCHITECTURE ART;