test_stream.vhd

设计一个模块

library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture arch_test of test is

component code_stream is
generic(for_detec:std_logic_vector:="11100");
port(clk:in std_logic;
	 reset:in std_logic;
	 datain:in std_logic;
	 pmatch:out std_logic);
end component;
signal clk,reset,datain,pmatch:std_logic;
begin
	U:code_stream port map(clk,reset,datain,pmatch); 
	
	clock:process
	begin
	clk<='0';
	wait for 5ns;
	clk<='1';
	wait for 5ns;
	end process clock;
	
	res:process
	begin
	reset<='0';
	wait for 160ns;
	reset<='1';
	wait for 20ns;		
	end process res;
	
	data:process
	begin
	datain<='0';
	wait for 10ns;
	datain<='1';
	wait for 30ns;
	datain<='0';
	wait for 30ns;		
	end process data;
	
	
end arch_test;
configuration cfg_test of test is
for arch_test
end for;
end cfg_test;