stream.awf

设计一个模块

$WAVE3
$RESOLUTION 1000
$SIGNAL 1 clk -1 0 SIGNAL 10000000
P 1 0 CS "0"
$SIGNAL 2 reset -1 0 SIGNAL 10000000
P 2 0 CS "0"
$SIGNAL 3 datain -1 0 SIGNAL 10000000
P 3 0 CS "0"
$SIGNAL 4 pmatch -1 0 SIGNAL 10000000
P 4 0 CS "0"
$BUS 5 5 stream -1 0 SIGNAL 10000000
P 5 0 CS "0"
$SIGNAL 6 "(4)" 5 0 SIGNAL 10000000
$SIGNAL 7 "(3)" 5 1 SIGNAL 10000000
$SIGNAL 8 "(2)" 5 2 SIGNAL 10000000
$SIGNAL 9 "(1)" 5 3 SIGNAL 10000000
$SIGNAL 10 "(0)" 5 4 SIGNAL 10000000
I 0 "e#9#std_logicc9 UX01ZWLH-"
S 1 0
S 2 0
S 3 0
S 4 0
I 1 "a#28#std_logic_vector(4 downto 0)1 ricd4 0 e#9#std_logicc9 UX01ZWLH-"
S 5 1
S 6 0
S 7 0
S 8 0
S 9 0
S 10 0
$WAVES 1
=0 T 0
=1 D 0 1
R 1 2000 =2 D 5k 1
$VALUES
V 1
U
R 2 1000 0 1
V 1
0
$END
$WAVES 2
*0
*1
R 2 55 =3 D 160k 1 =4 D 20k 1
$VALUES
V 1
U
R 2 55 0 1
V 1
0
$END
$WAVES 3
*0
*1
=5 D 10k 1
R 2 142 =6 D 30k 1 =7 D 40k 1
*6
$VALUES
V 1
U
R 2 143 0 1
V 1
0
$END
$WAVES 4
*0
*1
R 2 2 =8 D 60k 2 =9 D 10k 2
=10 D 130k 2
*9
*8
=11 D 5k 2
=12 D 65k 2
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
R 2 2 *9 *10
*9
*8
*9
*10
*9
*8
*11
*12
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
R 2 2 *9 *10
*9
*8
*9
*10
*9
*8
*11
*12
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
R 2 2 *9 *10
*9
*8
*9
*10
*9
*8
*11
*12
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
R 2 2 *9 *10
*9
*8
*9
*10
*9
*8
*11
*12
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
R 2 2 *9 *10
*9
*8
*9
*10
*9
*8
*11
*12
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
R 2 2 *9 *10
*9
*8
*9
*10
*9
*8
*11
*12
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
R 2 2 *9 *10
*9
*8
*9
*10
*9
*8
*11
*12
R 4 2 *9 *8 *9 *10
*9
*10
*9
*8
*9
*10
$VALUES
V 1
U
R 2 96 0 1
$END
$ENDWAVE