console.log

设计一个模块

Design: 18:03, 2005年11月4日
Design: Opening design "D:\VHDL_EXERCISE\Active_hdl\homework\hw3\hw3.adf"
ELBREAD: Elaboration process.
ELBREAD: Elaboration time 0.0 [s].
ELBREAD: Elaboration process.
ELBREAD: Elaboration time 0.0 [s].
VHDL file(s) detected
Compile...
File: .\src\test_stream.vhd
Compile Entity "test"
Entity "test" has been skipped - no difference detected.
Compile Architecture "arch_test" of Entity "test"
Compile Configuration "cfg_test"
Compile success 0 Errors 0 Warnings  Analysis time :  0.1 [s]
ELBREAD: Elaboration process.
ELBREAD: Elaboration time 0.0 [s].
KERNEL: Main thread initiated.
KERNEL: Kernel process initialization phase.
KERNEL: Time resolution set to 1ps.
ELAB2: Elaboration final pass...
ELAB2: Elaboration final pass complete - time: 0.1 [s].
KERNEL: Kernel process initialization done.
Allocation: Simulator allocated 97 kB (elbread=62 elab2=10 kernel=25 sdf=0)
18:03, 2005年11月4日
Simulation has been initialized
Selected Top-Level: test (arch_test)
Signal stream not found in design
KERNEL: stopped at time: 10 us
Evaluation Version : 10us simulation time has been reached.  Contact Aldec for ordering information - [e-mail]
Design Explorer: Shortcut to "D:\VHDL_EXERCISE\Active_hdl\homework\hw4\hw4.adf" design added.