sub_full.vhd

来自「该程序实现的N位全减器」· VHDL 代码 · 共 31 行

Entity sub_full is
port(
	 x,y:in bit;
     b_in:in bit;
	 b_out: out bit;
	 z:out bit
	 );
End sub_full;

Architecture sub_full of sub_full is

begin 
process(x,y,b_in)
begin
	case bit_vector'(x&y&b_in) is
	when"000" => z<='0';b_out<='0';
	when"001" => z<='1';b_out<='1';
	when"010" => z<='1';b_out<='1';
	when"011" => z<='0';b_out<='1';
	when"100" => z<='1';b_out<='0';
	when"101" => z<='0';b_out<='0';
	when"110" => z<='0';b_out<='0';
	when"111" => z<='1';b_out<='1';
	end case;			
end process;



end sub_full;