filter.vhd

用verilog实现滤波器的功能

  SIGNAL add_temp_27                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum29                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_28                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum30                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_29                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum31                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_30                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum32                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_31                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum33                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_32                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum34                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_33                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum35                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_34                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum36                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_35                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum37                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_36                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum38                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_37                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum39                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_38                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum40                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_39                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum41                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_40                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum42                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_41                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum43                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_42                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum44                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_43                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum45                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_44                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum46                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_45                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum47                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_46                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum48                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_47                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum49                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_48                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL sum50                            : signed(39 DOWNTO 0); -- sfix40_En31
  SIGNAL add_temp_49                      : signed(40 DOWNTO 0); -- sfix41_En31
  SIGNAL output_typeconvert               : signed(15 DOWNTO 0); -- sfix16_En31
  SIGNAL output_register                  : signed(15 DOWNTO 0); -- sfix16_En31


BEGIN

  -- Block Statements
  Delay_Pipeline_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      delay_pipeline(0 TO 49) <= (OTHERS => (OTHERS => '0'));
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        delay_pipeline(0) <= signed(filter_in);
        delay_pipeline(1 TO 49) <= delay_pipeline(0 TO 48);
      END IF;
    END IF; 
  END PROCESS Delay_Pipeline_process;

  filter_in_regtype <= signed(filter_in);

  product51 <= delay_pipeline(49) * coeff51;

  product50 <= delay_pipeline(48) * coeff50;

  product49 <= delay_pipeline(47) * coeff49;

  product48 <= delay_pipeline(46) * coeff48;

  product47 <= delay_pipeline(45) * coeff47;

  product46 <= delay_pipeline(44) * coeff46;

  product45 <= delay_pipeline(43) * coeff45;

  product44 <= delay_pipeline(42) * coeff44;

  product43 <= delay_pipeline(41) * coeff43;

  product42 <= delay_pipeline(40) * coeff42;

  product41 <= delay_pipeline(39) * coeff41;

  product40 <= delay_pipeline(38) * coeff40;

  product39 <= delay_pipeline(37) * coeff39;

  product38 <= delay_pipeline(36) * coeff38;

  product37 <= delay_pipeline(35) * coeff37;

  product36 <= delay_pipeline(34) * coeff36;

  product35 <= delay_pipeline(33) * coeff35;

  product34 <= delay_pipeline(32) * coeff34;

  product33 <= delay_pipeline(31) * coeff33;

  product32 <= delay_pipeline(30) * coeff32;

  product31 <= delay_pipeline(29) * coeff31;

  product30 <= delay_pipeline(28) * coeff30;

  product29 <= delay_pipeline(27) * coeff29;

  product28 <= delay_pipeline(26) * coeff28;

  product27 <= delay_pipeline(25) * coeff27;

  product26 <= delay_pipeline(24) * coeff26;

  product25 <= delay_pipeline(23) * coeff25;

  product24 <= delay_pipeline(22) * coeff24;

  product23 <= delay_pipeline(21) * coeff23;

  product22 <= delay_pipeline(20) * coeff22;

  product21 <= delay_pipeline(19) * coeff21;

  product20 <= delay_pipeline(18) * coeff20;

  product19 <= delay_pipeline(17) * coeff19;

  product18 <= delay_pipeline(16) * coeff18;

  product17 <= delay_pipeline(15) * coeff17;

  product16 <= delay_pipeline(14) * coeff16;

  product15 <= delay_pipeline(13) * coeff15;

  product14 <= delay_pipeline(12) * coeff14;

  product13 <= delay_pipeline(11) * coeff13;

  product12 <= delay_pipeline(10) * coeff12;

  product11 <= delay_pipeline(9) * coeff11;

  product10 <= delay_pipeline(8) * coeff10;

  product9 <= delay_pipeline(7) * coeff9;

  product8 <= delay_pipeline(6) * coeff8;

  product7 <= delay_pipeline(5) * coeff7;

  product6 <= delay_pipeline(4) * coeff6;

  product5 <= delay_pipeline(3) * coeff5;

  product4 <= delay_pipeline(2) * coeff4;

  product3 <= delay_pipeline(1) * coeff3;

  product2 <= delay_pipeline(0) * coeff2;

  mul_temp <= filter_in_regtype * coeff1;
  product1 <= resize( mul_temp, 40);

  add_temp <= resize(product1, 41) + resize(product2, 41);
  sum1 <= (39 => '0', OTHERS => '1') WHEN add_temp(40) = '0' AND add_temp(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp(40) = '1' AND add_temp(39) /= '1'
      ELSE (add_temp(39 DOWNTO 0));

  add_temp_1 <= resize(sum1, 41) + resize(product3, 41);
  sum2 <= (39 => '0', OTHERS => '1') WHEN add_temp_1(40) = '0' AND add_temp_1(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_1(40) = '1' AND add_temp_1(39) /= '1'
      ELSE (add_temp_1(39 DOWNTO 0));

  add_temp_2 <= resize(sum2, 41) + resize(product4, 41);
  sum3 <= (39 => '0', OTHERS => '1') WHEN add_temp_2(40) = '0' AND add_temp_2(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_2(40) = '1' AND add_temp_2(39) /= '1'
      ELSE (add_temp_2(39 DOWNTO 0));

  add_temp_3 <= resize(sum3, 41) + resize(product5, 41);
  sum4 <= (39 => '0', OTHERS => '1') WHEN add_temp_3(40) = '0' AND add_temp_3(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_3(40) = '1' AND add_temp_3(39) /= '1'
      ELSE (add_temp_3(39 DOWNTO 0));

  add_temp_4 <= resize(sum4, 41) + resize(product6, 41);
  sum5 <= (39 => '0', OTHERS => '1') WHEN add_temp_4(40) = '0' AND add_temp_4(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_4(40) = '1' AND add_temp_4(39) /= '1'
      ELSE (add_temp_4(39 DOWNTO 0));

  add_temp_5 <= resize(sum5, 41) + resize(product7, 41);
  sum6 <= (39 => '0', OTHERS => '1') WHEN add_temp_5(40) = '0' AND add_temp_5(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_5(40) = '1' AND add_temp_5(39) /= '1'
      ELSE (add_temp_5(39 DOWNTO 0));

  add_temp_6 <= resize(sum6, 41) + resize(product8, 41);
  sum7 <= (39 => '0', OTHERS => '1') WHEN add_temp_6(40) = '0' AND add_temp_6(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_6(40) = '1' AND add_temp_6(39) /= '1'
      ELSE (add_temp_6(39 DOWNTO 0));

  add_temp_7 <= resize(sum7, 41) + resize(product9, 41);
  sum8 <= (39 => '0', OTHERS => '1') WHEN add_temp_7(40) = '0' AND add_temp_7(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_7(40) = '1' AND add_temp_7(39) /= '1'
      ELSE (add_temp_7(39 DOWNTO 0));

  add_temp_8 <= resize(sum8, 41) + resize(product10, 41);
  sum9 <= (39 => '0', OTHERS => '1') WHEN add_temp_8(40) = '0' AND add_temp_8(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_8(40) = '1' AND add_temp_8(39) /= '1'
      ELSE (add_temp_8(39 DOWNTO 0));

  add_temp_9 <= resize(sum9, 41) + resize(product11, 41);
  sum10 <= (39 => '0', OTHERS => '1') WHEN add_temp_9(40) = '0' AND add_temp_9(39) /= '0'
      ELSE (39 => '1', OTHERS => '0') WHEN add_temp_9(40) = '1' AND add_temp_9(39) /= '1'
      ELSE (add_temp_9(39 DOWNTO 0));

  add_temp_10 <= resize(sum10, 41) + resize(product12, 41);