filter_tb.vhd

用verilog实现滤波器的功能

-- -------------------------------------------------------------
--
-- Module: filter_tb
--
-- Generated by MATLAB(R) 7.0.4 and the Filter Design HDL Coder 1.2.
--
-- Generated on: 2005-11-03 18:55:48
--
-- -------------------------------------------------------------

-- -------------------------------------------------------------
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- AddInputRegister: Off
-- TestBenchStimulus: impulse step ramp chirp noise 
--
-- Filter Settings:
--
-- Discrete-Time FIR Filter (real)
-- -------------------------------
-- Filter Structure  : Direct-Form FIR
-- Filter Length     : 51
-- Stable            : Yes
-- Linear Phase      : Yes (Type 1)
-- Arithmetic        : fixed
-- Numerator         : s16,16 -> [-5.000000e-001 5.000000e-001)
-- Input             : s16,15 -> [-1 1)
-- Filter Internals  : Specify Precision
--   Output          : s16,31 -> [-1.525879e-005 1.525879e-005)
--   Product         : s32,31 -> [-1 1)
--   Accumulator     : s40,31 -> [-256 256)
--   Round Mode      : floor
--   Overflow Mode   : saturate
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

ENTITY filter_tb IS

END filter_tb;


----------------------------------------------------------------
ARCHITECTURE test OF filter_tb IS
  COMPONENT filter
   PORT( clk                             :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_out                      :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En31
         );
    END COMPONENT;

  FOR ALL : filter
    USE ENTITY work.filter(rtl);

  FUNCTION to_hex( x : IN std_logic_vector) RETURN string IS
    VARIABLE result  : STRING(1 TO 256); -- 1024 bits max
    VARIABLE i       : INTEGER;
    VARIABLE imod    : INTEGER;
    VARIABLE j       : INTEGER;
    VARIABLE newx    : std_logic_vector(1023 DOWNTO 0);
    BEGIN
      newx := (OTHERS => '0');
      newx(x'RANGE) := x;
      i := x'LENGTH-1;
      imod := x'LENGTH MOD 4;
      IF    imod = 1 THEN i := i+3;
      ELSIF imod = 2 THEN i := i+2;
      ELSIF imod = 3 THEN i := i+1;
      END IF;
      j := 1;
      WHILE i >= 3 LOOP
        IF    newx(i DOWNTO (i-3)) = "0000" THEN result(j) := '0';
        ELSIF newx(i DOWNTO (i-3)) = "0001" THEN result(j) := '1';
        ELSIF newx(i DOWNTO (i-3)) = "0010" THEN result(j) := '2';
        ELSIF newx(i DOWNTO (i-3)) = "0011" THEN result(j) := '3';
        ELSIF newx(i DOWNTO (i-3)) = "0100" THEN result(j) := '4';
        ELSIF newx(i DOWNTO (i-3)) = "0101" THEN result(j) := '5';
        ELSIF newx(i DOWNTO (i-3)) = "0110" THEN result(j) := '6';
        ELSIF newx(i DOWNTO (i-3)) = "0111" THEN result(j) := '7';
        ELSIF newx(i DOWNTO (i-3)) = "1000" THEN result(j) := '8';
        ELSIF newx(i DOWNTO (i-3)) = "1001" THEN result(j) := '9';
        ELSIF newx(i DOWNTO (i-3)) = "1010" THEN result(j) := 'A';
        ELSIF newx(i DOWNTO (i-3)) = "1011" THEN result(j) := 'B';
        ELSIF newx(i DOWNTO (i-3)) = "1100" THEN result(j) := 'C';
        ELSIF newx(i DOWNTO (i-3)) = "1101" THEN result(j) := 'D';
        ELSIF newx(i DOWNTO (i-3)) = "1110" THEN result(j) := 'E';
        ELSIF newx(i DOWNTO (i-3)) = "1111" THEN result(j) := 'F';
        ELSE result(j) := 'X';
        END IF;

        i := i-4;
        j := j+1;
      END LOOP;
      RETURN result(1 TO j-1);
    END;

  FUNCTION to_hex( x : IN bit_vector ) RETURN string IS
    BEGIN
      RETURN to_hex( to_stdlogicvector(x) );
    END;

  -- Type Definitions
  TYPE filter_in_table IS ARRAY (0 TO 3428) OF std_logic_vector(15 DOWNTO 0);
  TYPE filter_out_table IS ARRAY (0 TO 3428) OF std_logic_vector(15 DOWNTO 0);
  -- Constants
  CONSTANT filter_in_force : filter_in_table :=
    (
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),
     to_stdlogicvector(bit_vector'(X"7fff"))(15 DOWNTO 0),