clkpro_new.v

采用Verilog HDL设计

/*时钟分频子模块，用于将20MHz时钟分频为6MHz和4Hz。 */
module  clkpro_new(clk,clk_6M,clk_4);
  input clk; 							//系统时钟，f= 20MHz
  output clk_6M,clk_4;					//in fact 6.67MHz
  parameter
	clk6M_cnt_M=2,
	clk4_cnt_M=5000000-1 //2^23=8388608
    ;

  reg clk_6M,clk_4;
  reg [2:0] clk6M_cnt;//0-12,counter for fas_set
  reg [22:0] clk4_cnt;//0-49,cnt for hlf_sec
  
	//produce the clk_6M    实际为6.67MHz
  always@(posedge clk )
    if(clk6M_cnt>=clk6M_cnt_M)
	  begin
		clk6M_cnt<=0;
		clk_6M<=1;
	  end
	else
	  begin
		clk6M_cnt<=clk6M_cnt+1;
		clk_6M<=0;
	  end
    //produce the clk_4
  always@(posedge clk )
    if(clk4_cnt>=clk4_cnt_M)
	  begin
		clk4_cnt<=0;
		clk_4<=1;
	  end
	else
	  begin
		clk4_cnt<=clk4_cnt+1;
		clk_4<=0;
	  end

endmodule