📄 clkdiv.rpt
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-- Equation name is 'clk4_cnt20', location is LC5_B10, type is buried.
clk4_cnt20 = DFFE( _EQ020, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ020 = clk4_cnt20 & !_LC2_B12 & !_LC4_B10
# !clk4_cnt20 & !_LC2_B12 & _LC4_B10;
-- Node name is ':104' = 'clk4_cnt21'
-- Equation name is 'clk4_cnt21', location is LC6_B10, type is buried.
clk4_cnt21 = DFFE( _EQ021, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ021 = !clk4_cnt20 & clk4_cnt21 & !_LC2_B12
# clk4_cnt21 & !_LC2_B12 & !_LC4_B10
# clk4_cnt20 & !clk4_cnt21 & !_LC2_B12 & _LC4_B10;
-- Node name is ':103' = 'clk4_cnt22'
-- Equation name is 'clk4_cnt22', location is LC8_B10, type is buried.
clk4_cnt22 = DFFE( _EQ022, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ022 = !clk4_cnt21 & clk4_cnt22 & !_LC2_B12
# clk4_cnt22 & !_LC2_B12 & !_LC7_B10
# clk4_cnt21 & !clk4_cnt22 & !_LC2_B12 & _LC7_B10;
-- Node name is 'clk_4'
-- Equation name is 'clk_4', type is output
clk_4 = _LC1_B2;
-- Node name is 'clk_6M'
-- Equation name is 'clk_6M', type is output
clk_6M = _LC7_B13;
-- Node name is ':9' = 'clk6M_cnt0'
-- Equation name is 'clk6M_cnt0', location is LC2_B13, type is buried.
clk6M_cnt0 = DFFE( _EQ023, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ023 = !clk6M_cnt0 & !clk6M_cnt1;
-- Node name is ':8' = 'clk6M_cnt1'
-- Equation name is 'clk6M_cnt1', location is LC1_B13, type is buried.
clk6M_cnt1 = DFFE( _EQ024, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ024 = clk6M_cnt0 & !clk6M_cnt1;
-- Node name is '|lpm_add_sub:131|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B12', type is buried
_LC3_B12 = LCELL( _EQ025);
_EQ025 = clk4_cnt0 & clk4_cnt1 & clk4_cnt2;
-- Node name is '|lpm_add_sub:131|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = LCELL( _EQ026);
_EQ026 = clk4_cnt3 & clk4_cnt4 & _LC3_B12;
-- Node name is '|lpm_add_sub:131|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ027);
_EQ027 = clk4_cnt5 & _LC1_B12;
-- Node name is '|lpm_add_sub:131|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ028);
_EQ028 = clk4_cnt6 & clk4_cnt7 & _LC8_B2;
-- Node name is '|lpm_add_sub:131|addcore:adder|:163' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ029);
_EQ029 = clk4_cnt8 & clk4_cnt9 & _LC3_B7;
-- Node name is '|lpm_add_sub:131|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = LCELL( _EQ030);
_EQ030 = clk4_cnt10 & clk4_cnt11 & _LC8_B7;
-- Node name is '|lpm_add_sub:131|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ031);
_EQ031 = clk4_cnt12 & clk4_cnt13 & _LC4_B9;
-- Node name is '|lpm_add_sub:131|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ032);
_EQ032 = clk4_cnt14 & _LC1_B9;
-- Node name is '|lpm_add_sub:131|addcore:adder|:191' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ033);
_EQ033 = clk4_cnt14 & clk4_cnt15 & clk4_cnt16 & _LC1_B9;
-- Node name is '|lpm_add_sub:131|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ034);
_EQ034 = clk4_cnt17 & _LC1_B1;
-- Node name is '|lpm_add_sub:131|addcore:adder|:203' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ035);
_EQ035 = clk4_cnt18 & clk4_cnt19 & _LC5_B1;
-- Node name is '|lpm_add_sub:131|addcore:adder|:207' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = LCELL( _EQ036);
_EQ036 = clk4_cnt20 & _LC4_B10;
-- Node name is ':26'
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = DFFE( _EQ037, GLOBAL( clk), VCC, VCC, VCC);
_EQ037 = clk6M_cnt0 & !clk6M_cnt1 & !clr;
-- Node name is '~28~1'
-- Equation name is '~28~1', location is LC2_B9, type is buried.
-- synthesized logic cell
_LC2_B9 = LCELL( _EQ038);
_EQ038 = clk4_cnt11
# clk4_cnt12
# !clk4_cnt13
# clk4_cnt14;
-- Node name is '~28~2'
-- Equation name is '~28~2', location is LC2_B7, type is buried.
-- synthesized logic cell
_LC2_B7 = LCELL( _EQ039);
_EQ039 = !clk4_cnt7
# !clk4_cnt8
# clk4_cnt9
# !clk4_cnt10;
-- Node name is '~28~3'
-- Equation name is '~28~3', location is LC1_B7, type is buried.
-- synthesized logic cell
_LC1_B7 = LCELL( _EQ040);
_EQ040 = _LC2_B9
# _LC2_B7
# clk4_cnt5
# clk4_cnt6;
-- Node name is '~28~4'
-- Equation name is '~28~4', location is LC2_B10, type is buried.
-- synthesized logic cell
_LC2_B10 = LCELL( _EQ041);
_EQ041 = clk4_cnt19
# clk4_cnt20
# !clk4_cnt21
# clk4_cnt22;
-- Node name is '~28~5'
-- Equation name is '~28~5', location is LC6_B1, type is buried.
-- synthesized logic cell
_LC6_B1 = LCELL( _EQ042);
_EQ042 = clk4_cnt15
# clk4_cnt16
# !clk4_cnt17
# !clk4_cnt18;
-- Node name is ':28'
-- Equation name is '_LC2_B12', type is buried
!_LC2_B12 = _LC2_B12~NOT;
_LC2_B12~NOT = LCELL( _EQ043);
_EQ043 = _LC1_B7
# _LC2_B10
# _LC6_B1
# !_LC1_B12;
-- Node name is ':127'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = DFFE(!_LC1_B2, GLOBAL( clk), VCC, VCC, !_LC3_B2);
-- Node name is ':129'
-- Equation name is '_LC3_B2', type is buried
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ044);
_EQ044 = !clr & _LC2_B12;
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkdiv.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,362K
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