📄 clkdiv.rpt
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IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 12 AND2 0 3 0 3 |lpm_add_sub:131|addcore:adder|:135
- 1 - B 12 AND2 0 3 0 3 |lpm_add_sub:131|addcore:adder|:143
- 8 - B 02 AND2 0 2 0 3 |lpm_add_sub:131|addcore:adder|:147
- 3 - B 07 AND2 0 3 0 3 |lpm_add_sub:131|addcore:adder|:155
- 8 - B 07 AND2 0 3 0 3 |lpm_add_sub:131|addcore:adder|:163
- 4 - B 09 AND2 0 3 0 3 |lpm_add_sub:131|addcore:adder|:171
- 1 - B 09 AND2 0 3 0 4 |lpm_add_sub:131|addcore:adder|:179
- 3 - B 01 AND2 0 2 0 1 |lpm_add_sub:131|addcore:adder|:183
- 1 - B 01 AND2 0 4 0 2 |lpm_add_sub:131|addcore:adder|:191
- 5 - B 01 AND2 0 2 0 3 |lpm_add_sub:131|addcore:adder|:195
- 4 - B 10 AND2 0 3 0 3 |lpm_add_sub:131|addcore:adder|:203
- 7 - B 10 AND2 0 2 0 1 |lpm_add_sub:131|addcore:adder|:207
- 1 - B 13 DFFE + 0 1 0 2 clk6M_cnt1 (:8)
- 2 - B 13 DFFE + 0 1 0 2 clk6M_cnt0 (:9)
- 7 - B 13 DFFE + 1 2 1 0 :26
- 2 - B 09 OR2 s 0 4 0 1 ~28~1
- 2 - B 07 OR2 s 0 4 0 1 ~28~2
- 1 - B 07 OR2 s 0 4 0 1 ~28~3
- 2 - B 10 OR2 s 0 4 0 1 ~28~4
- 6 - B 01 OR2 s 0 4 0 1 ~28~5
- 2 - B 12 OR2 ! 0 4 0 23 :28
- 8 - B 10 DFFE + 0 3 0 1 clk4_cnt22 (:103)
- 6 - B 10 DFFE + 0 3 0 2 clk4_cnt21 (:104)
- 5 - B 10 DFFE + 0 2 0 3 clk4_cnt20 (:105)
- 3 - B 10 DFFE + 0 3 0 2 clk4_cnt19 (:106)
- 1 - B 10 DFFE + 0 2 0 3 clk4_cnt18 (:107)
- 8 - B 01 DFFE + 0 2 0 2 clk4_cnt17 (:108)
- 7 - B 01 DFFE + 0 3 0 2 clk4_cnt16 (:109)
- 2 - B 01 DFFE + 0 3 0 3 clk4_cnt15 (:110)
- 4 - B 01 DFFE + 0 2 0 4 clk4_cnt14 (:111)
- 7 - B 09 DFFE + 0 3 0 2 clk4_cnt13 (:112)
- 6 - B 09 DFFE + 0 2 0 3 clk4_cnt12 (:113)
- 3 - B 09 DFFE + 0 3 0 2 clk4_cnt11 (:114)
- 5 - B 09 DFFE + 0 2 0 3 clk4_cnt10 (:115)
- 6 - B 07 DFFE + 0 3 0 2 clk4_cnt9 (:116)
- 5 - B 07 DFFE + 0 2 0 3 clk4_cnt8 (:117)
- 4 - B 07 DFFE + 0 3 0 2 clk4_cnt7 (:118)
- 7 - B 07 DFFE + 0 2 0 3 clk4_cnt6 (:119)
- 2 - B 02 DFFE + 0 2 0 2 clk4_cnt5 (:120)
- 8 - B 12 DFFE + 0 3 0 1 clk4_cnt4 (:121)
- 7 - B 12 DFFE + 0 2 0 2 clk4_cnt3 (:122)
- 6 - B 12 DFFE + 0 3 0 1 clk4_cnt2 (:123)
- 4 - B 12 DFFE + 0 2 0 2 clk4_cnt1 (:124)
- 5 - B 12 DFFE + 0 0 0 3 clk4_cnt0 (:125)
- 1 - B 02 DFFE + 0 1 1 0 :127
- 3 - B 02 AND2 ! 1 1 0 1 :129
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkdiv.rpt
clkdiv
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 15/ 48( 31%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkdiv.rpt
clkdiv
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 27 clk
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkdiv.rpt
clkdiv
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 27 clr
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkdiv.rpt
clkdiv
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is ':125' = 'clk4_cnt0'
-- Equation name is 'clk4_cnt0', location is LC5_B12, type is buried.
clk4_cnt0 = DFFE(!clk4_cnt0, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
-- Node name is ':124' = 'clk4_cnt1'
-- Equation name is 'clk4_cnt1', location is LC4_B12, type is buried.
clk4_cnt1 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = clk4_cnt0 & !clk4_cnt1 & !_LC2_B12
# !clk4_cnt0 & clk4_cnt1 & !_LC2_B12;
-- Node name is ':123' = 'clk4_cnt2'
-- Equation name is 'clk4_cnt2', location is LC6_B12, type is buried.
clk4_cnt2 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !clk4_cnt0 & clk4_cnt2 & !_LC2_B12
# !clk4_cnt1 & clk4_cnt2 & !_LC2_B12
# clk4_cnt0 & clk4_cnt1 & !clk4_cnt2 & !_LC2_B12;
-- Node name is ':122' = 'clk4_cnt3'
-- Equation name is 'clk4_cnt3', location is LC7_B12, type is buried.
clk4_cnt3 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = clk4_cnt3 & !_LC2_B12 & !_LC3_B12
# !clk4_cnt3 & !_LC2_B12 & _LC3_B12;
-- Node name is ':121' = 'clk4_cnt4'
-- Equation name is 'clk4_cnt4', location is LC8_B12, type is buried.
clk4_cnt4 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = !clk4_cnt3 & clk4_cnt4 & !_LC2_B12
# clk4_cnt4 & !_LC2_B12 & !_LC3_B12
# clk4_cnt3 & !clk4_cnt4 & !_LC2_B12 & _LC3_B12;
-- Node name is ':120' = 'clk4_cnt5'
-- Equation name is 'clk4_cnt5', location is LC2_B2, type is buried.
clk4_cnt5 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = clk4_cnt5 & !_LC1_B12 & !_LC2_B12
# !clk4_cnt5 & _LC1_B12 & !_LC2_B12;
-- Node name is ':119' = 'clk4_cnt6'
-- Equation name is 'clk4_cnt6', location is LC7_B7, type is buried.
clk4_cnt6 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = clk4_cnt6 & !_LC2_B12 & !_LC8_B2
# !clk4_cnt6 & !_LC2_B12 & _LC8_B2;
-- Node name is ':118' = 'clk4_cnt7'
-- Equation name is 'clk4_cnt7', location is LC4_B7, type is buried.
clk4_cnt7 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ007 = !clk4_cnt6 & clk4_cnt7 & !_LC2_B12
# clk4_cnt7 & !_LC2_B12 & !_LC8_B2
# clk4_cnt6 & !clk4_cnt7 & !_LC2_B12 & _LC8_B2;
-- Node name is ':117' = 'clk4_cnt8'
-- Equation name is 'clk4_cnt8', location is LC5_B7, type is buried.
clk4_cnt8 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ008 = clk4_cnt8 & !_LC2_B12 & !_LC3_B7
# !clk4_cnt8 & !_LC2_B12 & _LC3_B7;
-- Node name is ':116' = 'clk4_cnt9'
-- Equation name is 'clk4_cnt9', location is LC6_B7, type is buried.
clk4_cnt9 = DFFE( _EQ009, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ009 = !clk4_cnt8 & clk4_cnt9 & !_LC2_B12
# clk4_cnt9 & !_LC2_B12 & !_LC3_B7
# clk4_cnt8 & !clk4_cnt9 & !_LC2_B12 & _LC3_B7;
-- Node name is ':115' = 'clk4_cnt10'
-- Equation name is 'clk4_cnt10', location is LC5_B9, type is buried.
clk4_cnt10 = DFFE( _EQ010, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ010 = clk4_cnt10 & !_LC2_B12 & !_LC8_B7
# !clk4_cnt10 & !_LC2_B12 & _LC8_B7;
-- Node name is ':114' = 'clk4_cnt11'
-- Equation name is 'clk4_cnt11', location is LC3_B9, type is buried.
clk4_cnt11 = DFFE( _EQ011, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ011 = !clk4_cnt10 & clk4_cnt11 & !_LC2_B12
# clk4_cnt11 & !_LC2_B12 & !_LC8_B7
# clk4_cnt10 & !clk4_cnt11 & !_LC2_B12 & _LC8_B7;
-- Node name is ':113' = 'clk4_cnt12'
-- Equation name is 'clk4_cnt12', location is LC6_B9, type is buried.
clk4_cnt12 = DFFE( _EQ012, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ012 = clk4_cnt12 & !_LC2_B12 & !_LC4_B9
# !clk4_cnt12 & !_LC2_B12 & _LC4_B9;
-- Node name is ':112' = 'clk4_cnt13'
-- Equation name is 'clk4_cnt13', location is LC7_B9, type is buried.
clk4_cnt13 = DFFE( _EQ013, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ013 = !clk4_cnt12 & clk4_cnt13 & !_LC2_B12
# clk4_cnt13 & !_LC2_B12 & !_LC4_B9
# clk4_cnt12 & !clk4_cnt13 & !_LC2_B12 & _LC4_B9;
-- Node name is ':111' = 'clk4_cnt14'
-- Equation name is 'clk4_cnt14', location is LC4_B1, type is buried.
clk4_cnt14 = DFFE( _EQ014, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ014 = clk4_cnt14 & !_LC1_B9 & !_LC2_B12
# !clk4_cnt14 & _LC1_B9 & !_LC2_B12;
-- Node name is ':110' = 'clk4_cnt15'
-- Equation name is 'clk4_cnt15', location is LC2_B1, type is buried.
clk4_cnt15 = DFFE( _EQ015, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ015 = !clk4_cnt14 & clk4_cnt15 & !_LC2_B12
# clk4_cnt15 & !_LC1_B9 & !_LC2_B12
# clk4_cnt14 & !clk4_cnt15 & _LC1_B9 & !_LC2_B12;
-- Node name is ':109' = 'clk4_cnt16'
-- Equation name is 'clk4_cnt16', location is LC7_B1, type is buried.
clk4_cnt16 = DFFE( _EQ016, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ016 = !clk4_cnt15 & clk4_cnt16 & !_LC2_B12
# clk4_cnt16 & !_LC2_B12 & !_LC3_B1
# clk4_cnt15 & !clk4_cnt16 & !_LC2_B12 & _LC3_B1;
-- Node name is ':108' = 'clk4_cnt17'
-- Equation name is 'clk4_cnt17', location is LC8_B1, type is buried.
clk4_cnt17 = DFFE( _EQ017, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ017 = clk4_cnt17 & !_LC1_B1 & !_LC2_B12
# !clk4_cnt17 & _LC1_B1 & !_LC2_B12;
-- Node name is ':107' = 'clk4_cnt18'
-- Equation name is 'clk4_cnt18', location is LC1_B10, type is buried.
clk4_cnt18 = DFFE( _EQ018, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ018 = clk4_cnt18 & !_LC2_B12 & !_LC5_B1
# !clk4_cnt18 & !_LC2_B12 & _LC5_B1;
-- Node name is ':106' = 'clk4_cnt19'
-- Equation name is 'clk4_cnt19', location is LC3_B10, type is buried.
clk4_cnt19 = DFFE( _EQ019, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ019 = !clk4_cnt18 & clk4_cnt19 & !_LC2_B12
# clk4_cnt19 & !_LC2_B12 & !_LC5_B1
# clk4_cnt18 & !clk4_cnt19 & !_LC2_B12 & _LC5_B1;
-- Node name is ':105' = 'clk4_cnt20'
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