📄 clkpro.rpt
字号:
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkpro.rpt
clkpro
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 20 OR2 ! 0 3 0 2 |lpm_add_sub:241|addcore:adder|:135
- 1 - B 20 OR2 ! 0 2 0 4 |lpm_add_sub:241|addcore:adder|:139
- 6 - B 22 AND2 0 4 0 4 |lpm_add_sub:241|addcore:adder|:151
- 1 - B 15 AND2 0 2 0 1 |lpm_add_sub:241|addcore:adder|:155
- 5 - B 22 AND2 0 4 0 4 |lpm_add_sub:241|addcore:adder|:163
- 8 - B 19 AND2 0 3 0 1 |lpm_add_sub:241|addcore:adder|:171
- 1 - B 19 AND2 0 4 0 4 |lpm_add_sub:241|addcore:adder|:175
- 3 - B 17 AND2 0 3 0 1 |lpm_add_sub:241|addcore:adder|:183
- 6 - B 21 AND2 0 4 0 3 |lpm_add_sub:241|addcore:adder|:187
- 3 - B 21 AND2 0 3 0 4 |lpm_add_sub:241|addcore:adder|:195
- 4 - B 19 AND2 0 3 0 1 |lpm_add_sub:241|addcore:adder|:203
- 2 - B 15 AND2 0 4 0 2 |lpm_add_sub:241|addcore:adder|:207
- 2 - A 07 DFFE + 0 1 0 2 clk6M_cnt1 (:36)
- 1 - A 07 DFFE + 0 1 0 1 clk6M_cnt0 (:37)
- 7 - A 07 DFFE + 0 1 1 0 :41
- 7 - B 15 OR2 0 4 0 23 :51
- 2 - B 21 OR2 0 4 0 2 :66
- 5 - B 21 OR2 s 0 4 0 1 ~73~1
- 4 - B 21 OR2 0 4 0 1 :93
- 4 - B 22 OR2 0 4 0 1 :108
- 2 - B 22 AND2 0 3 0 1 :123
- 1 - B 22 OR2 0 3 0 2 :136
- 8 - B 15 DFFE + 0 3 0 2 clk4_cnt22 (:213)
- 4 - B 15 DFFE + 0 2 0 3 clk4_cnt21 (:214)
- 6 - B 15 DFFE + 0 2 0 3 clk4_cnt20 (:215)
- 7 - B 19 DFFE + 0 3 0 3 clk4_cnt19 (:216)
- 6 - B 19 DFFE + 0 2 0 4 clk4_cnt18 (:217)
- 8 - B 21 DFFE + 0 3 0 2 clk4_cnt17 (:218)
- 7 - B 21 DFFE + 0 2 0 3 clk4_cnt16 (:219)
- 2 - B 17 DFFE + 0 2 0 2 clk4_cnt15 (:220)
- 1 - B 21 DFFE + 0 3 0 3 clk4_cnt14 (:221)
- 1 - B 17 DFFE + 0 2 0 4 clk4_cnt13 (:222)
- 3 - B 19 DFFE + 0 2 0 2 clk4_cnt12 (:223)
- 5 - B 19 DFFE + 0 3 0 3 clk4_cnt11 (:224)
- 2 - B 19 DFFE + 0 2 0 4 clk4_cnt10 (:225)
- 8 - B 22 DFFE + 0 3 0 2 clk4_cnt9 (:226)
- 7 - B 22 DFFE + 0 3 0 3 clk4_cnt8 (:227)
- 5 - B 15 DFFE + 0 2 0 4 clk4_cnt7 (:228)
- 3 - B 22 DFFE + 0 2 0 2 clk4_cnt6 (:229)
- 2 - B 20 DFFE + 0 3 0 2 clk4_cnt5 (:230)
- 6 - B 20 DFFE + 0 2 0 3 clk4_cnt4 (:231)
- 8 - B 20 DFFE + 0 2 0 1 clk4_cnt3 (:232)
- 4 - B 20 DFFE + 0 3 0 1 clk4_cnt2 (:233)
- 7 - B 20 DFFE + 0 2 0 2 clk4_cnt1 (:234)
- 5 - B 20 DFFE + 0 1 0 3 clk4_cnt0 (:235)
- 3 - B 15 DFFE + 0 4 1 0 :239
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkpro.rpt
clkpro
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 22/ 48( 45%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkpro.rpt
clkpro
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 27 clk
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\clkpro.rpt
clkpro
** EQUATIONS **
clk : INPUT;
-- Node name is ':235' = 'clk4_cnt0'
-- Equation name is 'clk4_cnt0', location is LC5_B20, type is buried.
clk4_cnt0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !clk4_cnt0 & _LC7_B15;
-- Node name is ':234' = 'clk4_cnt1'
-- Equation name is 'clk4_cnt1', location is LC7_B20, type is buried.
clk4_cnt1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = clk4_cnt0 & !clk4_cnt1 & _LC7_B15
# !clk4_cnt0 & clk4_cnt1 & _LC7_B15;
-- Node name is ':233' = 'clk4_cnt2'
-- Equation name is 'clk4_cnt2', location is LC4_B20, type is buried.
clk4_cnt2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !clk4_cnt0 & clk4_cnt2 & _LC7_B15
# !clk4_cnt1 & clk4_cnt2 & _LC7_B15
# clk4_cnt0 & clk4_cnt1 & !clk4_cnt2 & _LC7_B15;
-- Node name is ':232' = 'clk4_cnt3'
-- Equation name is 'clk4_cnt3', location is LC8_B20, type is buried.
clk4_cnt3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = clk4_cnt3 & !_LC3_B20 & _LC7_B15
# !clk4_cnt3 & _LC3_B20 & _LC7_B15;
-- Node name is ':231' = 'clk4_cnt4'
-- Equation name is 'clk4_cnt4', location is LC6_B20, type is buried.
clk4_cnt4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = clk4_cnt4 & !_LC1_B20 & _LC7_B15
# !clk4_cnt4 & _LC1_B20 & _LC7_B15;
-- Node name is ':230' = 'clk4_cnt5'
-- Equation name is 'clk4_cnt5', location is LC2_B20, type is buried.
clk4_cnt5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !clk4_cnt4 & clk4_cnt5 & _LC7_B15
# clk4_cnt5 & !_LC1_B20 & _LC7_B15
# clk4_cnt4 & !clk4_cnt5 & _LC1_B20 & _LC7_B15;
-- Node name is ':229' = 'clk4_cnt6'
-- Equation name is 'clk4_cnt6', location is LC3_B22, type is buried.
clk4_cnt6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = clk4_cnt6 & _LC1_B22 & _LC7_B15
# !clk4_cnt6 & !_LC1_B22 & _LC7_B15;
-- Node name is ':228' = 'clk4_cnt7'
-- Equation name is 'clk4_cnt7', location is LC5_B15, type is buried.
clk4_cnt7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = clk4_cnt7 & !_LC6_B22 & _LC7_B15
# !clk4_cnt7 & _LC6_B22 & _LC7_B15;
-- Node name is ':227' = 'clk4_cnt8'
-- Equation name is 'clk4_cnt8', location is LC7_B22, type is buried.
clk4_cnt8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !clk4_cnt7 & clk4_cnt8 & _LC7_B15
# clk4_cnt8 & !_LC6_B22 & _LC7_B15
# clk4_cnt7 & !clk4_cnt8 & _LC6_B22 & _LC7_B15;
-- Node name is ':226' = 'clk4_cnt9'
-- Equation name is 'clk4_cnt9', location is LC8_B22, type is buried.
clk4_cnt9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !clk4_cnt8 & clk4_cnt9 & _LC7_B15
# clk4_cnt9 & !_LC1_B15 & _LC7_B15
# clk4_cnt8 & !clk4_cnt9 & _LC1_B15 & _LC7_B15;
-- Node name is ':225' = 'clk4_cnt10'
-- Equation name is 'clk4_cnt10', location is LC2_B19, type is buried.
clk4_cnt10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = clk4_cnt10 & !_LC5_B22 & _LC7_B15
# !clk4_cnt10 & _LC5_B22 & _LC7_B15;
-- Node name is ':224' = 'clk4_cnt11'
-- Equation name is 'clk4_cnt11', location is LC5_B19, type is buried.
clk4_cnt11 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !clk4_cnt10 & clk4_cnt11 & _LC7_B15
# clk4_cnt11 & !_LC5_B22 & _LC7_B15
# clk4_cnt10 & !clk4_cnt11 & _LC5_B22 & _LC7_B15;
-- Node name is ':223' = 'clk4_cnt12'
-- Equation name is 'clk4_cnt12', location is LC3_B19, type is buried.
clk4_cnt12 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = clk4_cnt12 & _LC7_B15 & !_LC8_B19
# !clk4_cnt12 & _LC7_B15 & _LC8_B19;
-- Node name is ':222' = 'clk4_cnt13'
-- Equation name is 'clk4_cnt13', location is LC1_B17, type is buried.
clk4_cnt13 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = clk4_cnt13 & !_LC1_B19 & _LC7_B15
# !clk4_cnt13 & _LC1_B19 & _LC7_B15;
-- Node name is ':221' = 'clk4_cnt14'
-- Equation name is 'clk4_cnt14', location is LC1_B21, type is buried.
clk4_cnt14 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !clk4_cnt13 & clk4_cnt14 & _LC7_B15
# clk4_cnt14 & !_LC1_B19 & _LC7_B15
# clk4_cnt13 & !clk4_cnt14 & _LC1_B19 & _LC7_B15;
-- Node name is ':220' = 'clk4_cnt15'
-- Equation name is 'clk4_cnt15', location is LC2_B17, type is buried.
clk4_cnt15 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = clk4_cnt15 & !_LC3_B17 & _LC7_B15
# !clk4_cnt15 & _LC3_B17 & _LC7_B15;
-- Node name is ':219' = 'clk4_cnt16'
-- Equation name is 'clk4_cnt16', location is LC7_B21, type is buried.
clk4_cnt16 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = clk4_cnt16 & !_LC6_B21 & _LC7_B15
# !clk4_cnt16 & _LC6_B21 & _LC7_B15;
-- Node name is ':218' = 'clk4_cnt17'
-- Equation name is 'clk4_cnt17', location is LC8_B21, type is buried.
clk4_cnt17 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = !clk4_cnt16 & clk4_cnt17 & _LC7_B15
# clk4_cnt17 & !_LC6_B21 & _LC7_B15
# clk4_cnt16 & !clk4_cnt17 & _LC6_B21 & _LC7_B15;
-- Node name is ':217' = 'clk4_cnt18'
-- Equation name is 'clk4_cnt18', location is LC6_B19, type is buried.
clk4_cnt18 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = clk4_cnt18 & !_LC3_B21 & _LC7_B15
# !clk4_cnt18 & _LC3_B21 & _LC7_B15;
-- Node name is ':216' = 'clk4_cnt19'
-- Equation name is 'clk4_cnt19', location is LC7_B19, type is buried.
clk4_cnt19 = DFFE( _EQ020, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = !clk4_cnt18 & clk4_cnt19 & _LC7_B15
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