musicpro_try.rpt

采用Verilog HDL设计

-- synthesized logic cell 
_LC4_A23 = LCELL( _EQ098);
  _EQ098 =  _LC2_A18 &  _LC6_A23
         #  _LC3_A23
         #  _LC5_A23;

-- Node name is '~1928~1' 
-- Equation name is '~1928~1', location is LC7_A21, type is buried.
-- synthesized logic cell 
_LC7_A21 = LCELL( _EQ099);
  _EQ099 = !counter2 &  _LC4_A21 &  _LC5_A18
         #  _LC5_A21;

-- Node name is '~1928~2' 
-- Equation name is '~1928~2', location is LC6_A21, type is buried.
-- synthesized logic cell 
_LC6_A21 = LCELL( _EQ100);
  _EQ100 =  _LC1_A21 &  _LC3_A21
         #  _LC7_A21
         #  _LC3_A21 &  _LC8_A21;

-- Node name is '~1934~1' 
-- Equation name is '~1934~1', location is LC6_A22, type is buried.
-- synthesized logic cell 
_LC6_A22 = LCELL( _EQ101);
  _EQ101 =  _LC5_A22
         # !counter5 &  _LC8_A17 &  _LC8_A23;

-- Node name is '~1934~2' 
-- Equation name is '~1934~2', location is LC1_A22, type is buried.
-- synthesized logic cell 
_LC1_A22 = LCELL( _EQ102);
  _EQ102 = !counter4 &  _LC6_A22
         # !counter4 & !counter5 &  _LC7_A22;

-- Node name is '~1934~3' 
-- Equation name is '~1934~3', location is LC4_A18, type is buried.
-- synthesized logic cell 
_LC4_A18 = LCELL( _EQ103);
  _EQ103 = !counter5 &  _LC2_A23
         #  _LC2_A18;

-- Node name is '~1934~4' 
-- Equation name is '~1934~4', location is LC4_A24, type is buried.
-- synthesized logic cell 
_LC4_A24 = LCELL( _EQ104);
  _EQ104 =  _LC1_A22
         #  counter2 &  _LC4_A18 &  _LC6_A20;

-- Node name is '~1934~5' 
-- Equation name is '~1934~5', location is LC5_A24, type is buried.
-- synthesized logic cell 
_LC5_A24 = LCELL( _EQ105);
  _EQ105 =  _LC1_A24 &  _LC6_A20
         # !counter1 &  _LC1_A24
         #  _LC4_A24;

-- Node name is ':1941' 
-- Equation name is '_LC3_A24', type is buried 
_LC3_A24 = DFFE( _EQ106, GLOBAL( clk_4), GLOBAL(!clr),  VCC,  VCC);
  _EQ106 =  _LC5_A24
         #  _LC6_A24
         #  _LC7_A24
         #  _LC4_A23;

-- Node name is ':1942' 
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = DFFE( _EQ107, GLOBAL( clk_4), GLOBAL(!clr),  VCC,  VCC);
  _EQ107 =  _LC7_A24
         #  _LC4_A23
         #  _LC6_A24
         #  _LC6_A21;

-- Node name is ':1943' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = DFFE( _EQ108, GLOBAL( clk_4), GLOBAL(!clr),  VCC,  VCC);
  _EQ108 =  _LC5_A24
         #  _LC6_A24
         #  _LC6_A21;

-- Node name is '~1956~1' 
-- Equation name is '~1956~1', location is LC1_B13, type is buried.
-- synthesized logic cell 
!_LC1_B13 = _LC1_B13~NOT;
_LC1_B13~NOT = LCELL( _EQ109);
  _EQ109 = !_LC1_B16 & !_LC3_A18 & !_LC4_A13 & !_LC6_A18;

-- Node name is ':1956' 
-- Equation name is '_LC5_B16', type is buried 
!_LC5_B16 = _LC5_B16~NOT;
_LC5_B16~NOT = LCELL( _EQ110);
  _EQ110 =  _LC3_A24
         # !_LC2_A24
         # !_LC8_A24
         #  _LC1_B13;

-- Node name is ':1983' 
-- Equation name is '_LC6_B16', type is buried 
_LC6_B16 = LCELL( _EQ111);
  _EQ111 = !_LC1_B13 & !_LC2_A24 &  _LC3_A24 &  _LC8_A24;

-- Node name is ':2010' 
-- Equation name is '_LC8_B16', type is buried 
!_LC8_B16 = _LC8_B16~NOT;
_LC8_B16~NOT = LCELL( _EQ112);
  _EQ112 =  _LC8_A24
         # !_LC2_A24
         # !_LC3_A24
         #  _LC1_B13;

-- Node name is ':2037' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = LCELL( _EQ113);
  _EQ113 = !_LC1_B13 &  _LC2_A24 &  _LC3_A24 &  _LC8_A24;

-- Node name is ':2064' 
-- Equation name is '_LC5_B13', type is buried 
_LC5_B13 = LCELL( _EQ114);
  _EQ114 =  _LC3_A18 & !_LC3_B16 & !_LC4_A13 & !_LC6_A18;

-- Node name is '~2091~1' 
-- Equation name is '~2091~1', location is LC3_B16, type is buried.
-- synthesized logic cell 
!_LC3_B16 = _LC3_B16~NOT;
_LC3_B16~NOT = LCELL( _EQ115);
  _EQ115 = !_LC1_B16 & !_LC2_A24 & !_LC3_A24 & !_LC8_A24;

-- Node name is ':2091' 
-- Equation name is '_LC3_B13', type is buried 
!_LC3_B13 = _LC3_B13~NOT;
_LC3_B13~NOT = LCELL( _EQ116);
  _EQ116 =  _LC6_A18
         #  _LC3_A18
         # !_LC4_A13
         #  _LC3_B16;

-- Node name is ':2118' 
-- Equation name is '_LC4_B13', type is buried 
_LC4_B13 = LCELL( _EQ117);
  _EQ117 =  _LC3_A18 & !_LC3_B16 &  _LC4_A13 & !_LC6_A18;

-- Node name is ':2145' 
-- Equation name is '_LC2_B13', type is buried 
!_LC2_B13 = _LC2_B13~NOT;
_LC2_B13~NOT = LCELL( _EQ118);
  _EQ118 = !_LC6_A18
         #  _LC4_A13
         # !_LC3_A18
         #  _LC3_B16;

-- Node name is ':2172' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = LCELL( _EQ119);
  _EQ119 = !_LC3_A18 & !_LC3_B16 &  _LC4_A13 &  _LC6_A18;

-- Node name is '~2199~1' 
-- Equation name is '~2199~1', location is LC2_B16, type is buried.
-- synthesized logic cell 
_LC2_B16 = LCELL( _EQ120);
  _EQ120 = !_LC1_B16
         #  _LC3_A24
         #  _LC2_A24
         #  _LC8_A24;

-- Node name is ':2199' 
-- Equation name is '_LC6_B13', type is buried 
!_LC6_B13 = _LC6_B13~NOT;
_LC6_B13~NOT = LCELL( _EQ121);
  _EQ121 =  _LC2_B16
         #  _LC4_A13
         #  _LC6_A18
         #  _LC3_A18;

-- Node name is '~2262~1' 
-- Equation name is '~2262~1', location is LC8_B15, type is buried.
-- synthesized logic cell 
!_LC8_B15 = _LC8_B15~NOT;
_LC8_B15~NOT = LCELL( _EQ122);
  _EQ122 =  _LC5_B13
         #  _LC4_B16;

-- Node name is '~2279~1' 
-- Equation name is '~2279~1', location is LC1_B18, type is buried.
-- synthesized logic cell 
!_LC1_B18 = _LC1_B18~NOT;
_LC1_B18~NOT = LCELL( _EQ123);
  _EQ123 = !_LC5_B18 & !_LC7_B13;

-- Node name is '~2279~2' 
-- Equation name is '~2279~2', location is LC2_B18, type is buried.
-- synthesized logic cell 
_LC2_B18 = LCELL( _EQ124);
  _EQ124 = !_LC1_B18 & !_LC4_B13 & !_LC5_B16 & !_LC6_B16;

-- Node name is '~2279~3' 
-- Equation name is '~2279~3', location is LC8_B13, type is buried.
-- synthesized logic cell 
_LC8_B13 = LCELL( _EQ125);
  _EQ125 = !_LC3_A18 & !_LC3_B16 & !_LC4_A13 & !_LC6_A18;

-- Node name is '~2279~4' 
-- Equation name is '~2279~4', location is LC8_B18, type is buried.
-- synthesized logic cell 
_LC8_B18 = LCELL( _EQ126);
  _EQ126 =  _LC2_B18 & !_LC2_B20 &  _LC8_B15
         #  _LC8_B13;

-- Node name is '~2280~1' 
-- Equation name is '~2280~1', location is LC1_B24, type is buried.
-- synthesized logic cell 
_LC1_B24 = LCELL( _EQ127);
  _EQ127 =  _LC5_B19
         #  _LC4_B13;

-- Node name is '~2281~1' 
-- Equation name is '~2281~1', location is LC2_B20, type is buried.
-- synthesized logic cell 
!_LC2_B20 = _LC2_B20~NOT;
_LC2_B20~NOT = LCELL( _EQ128);
  _EQ128 = !_LC3_B13 & !_LC8_B16;

-- Node name is '~2284~1' 
-- Equation name is '~2284~1', location is LC4_B19, type is buried.
-- synthesized logic cell 
_LC4_B19 = LCELL( _EQ129);
  _EQ129 =  _LC8_B18
         #  _LC7_B13;

-- Node name is '~2285~1' 
-- Equation name is '~2285~1', location is LC5_B19, type is buried.
-- synthesized logic cell 
_LC5_B19 = LCELL( _EQ130);
  _EQ130 =  _LC8_B18
         #  _LC5_B16;

-- Node name is '~2288~1' 
-- Equation name is '~2288~1', location is LC5_B18, type is buried.
-- synthesized logic cell 
!_LC5_B18 = _LC5_B18~NOT;
_LC5_B18~NOT = LCELL( _EQ131);
  _EQ131 = !_LC2_B13 & !_LC6_B13;

-- Node name is '~2289~1' 
-- Equation name is '~2289~1', location is LC3_B21, type is buried.
-- synthesized logic cell 
_LC3_B21 = LCELL( _EQ132);
  _EQ132 =  _LC4_B16
         #  _LC8_B16
         #  _LC2_B13
         #  _LC4_B13;

-- Node name is ':2383' 
-- Equation name is '_LC4_B7', type is buried 
_LC4_B7  = DFFE(!_LC4_B7,  _LC6_B19, GLOBAL(!clr),  VCC,  VCC);



Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_try.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimiz