📄 musicpro_try.rpt
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- 1 - A 17 AND2 0 3 0 4 |lpm_add_sub:2384|addcore:adder|:137
- 5 - A 17 OR2 0 2 0 1 |lpm_add_sub:2384|addcore:adder|:154
- 2 - B 14 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:95
- 1 - B 17 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:99
- 3 - B 17 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:103
- 2 - B 17 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:107
- 2 - B 21 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:111
- 8 - B 21 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:115
- 6 - B 18 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:119
- 1 - B 23 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:123
- 2 - B 23 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:127
- 8 - B 23 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:131
- 8 - B 14 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:135
- 1 - B 19 AND2 0 2 0 2 |lpm_add_sub:2385|addcore:adder|:139
- 6 - B 19 AND2 0 2 1 15 :18
- 4 - A 17 DFFE + 0 3 0 2 counter7 (:36)
- 3 - A 17 DFFE + 0 2 0 4 counter6 (:37)
- 2 - A 22 DFFE + 0 3 0 17 counter5 (:38)
- 8 - A 22 DFFE + 0 2 0 12 counter4 (:39)
- 7 - A 23 DFFE + 0 2 0 5 counter3 (:40)
- 8 - A 20 AND2 s 0 4 0 1 counter2~1 (~41~1)
- 2 - A 21 DFFE + 0 2 0 21 counter2 (:41)
- 5 - A 23 AND2 s 0 4 0 1 counter1~1 (~42~1)
- 5 - A 20 DFFE + 0 1 0 10 counter1 (:42)
- 1 - A 18 DFFE + 0 1 0 11 counter0 (:43)
- 3 - A 22 OR2 s 0 2 0 5 ~44~1
- 4 - A 22 OR2 ! 0 4 0 10 :44
- 6 - A 17 OR2 ! 0 4 0 1 :58
- 2 - A 20 OR2 0 3 0 4 :62
- 5 - A 18 AND2 0 2 0 4 :63
- 4 - A 21 AND2 s 0 3 0 1 ~72~1
- 1 - A 21 OR2 s 0 3 0 1 ~97~1
- 7 - A 17 OR2 s 0 4 0 1 ~97~2
- 2 - A 17 OR2 s 0 4 0 1 ~97~3
- 3 - A 21 OR2 s 0 4 0 1 ~97~4
- 5 - A 21 AND2 0 4 0 1 :122
- 8 - A 21 OR2 s 0 4 0 1 ~147~1
- 1 - A 20 OR2 s ! 0 2 0 4 ~197~1
- 5 - A 22 AND2 s 0 4 0 1 ~197~2
- 2 - A 18 AND2 s 0 3 0 3 ~247~1
- 7 - A 18 AND2 s 0 2 0 1 ~372~1
- 6 - A 20 AND2 s 0 2 0 3 ~422~1
- 3 - A 13 AND2 s 0 4 0 2 ~522~1
- 7 - A 22 AND2 s 0 2 0 1 ~572~1
- 5 - A 13 AND2 0 3 0 1 :572
- 7 - A 20 AND2 s 0 2 0 1 ~647~1
- 8 - A 16 AND2 s 0 2 0 1 ~947~1
- 4 - A 15 AND2 s 0 3 0 2 ~947~2
- 8 - A 17 OR2 s ! 0 2 0 4 ~1047~1
- 1 - A 23 OR2 s ! 0 2 0 8 ~1047~2
- 6 - A 13 AND2 s 0 3 0 1 ~1047~3
- 2 - A 23 AND2 s 0 3 0 5 ~1122~1
- 1 - A 24 AND2 s 0 3 0 1 ~1147~1
- 1 - B 16 DFFE + 0 4 1 3 :1375
- 5 - A 15 AND2 s 0 3 0 3 ~1644~1
- 1 - A 15 AND2 s 0 2 0 8 ~1644~2
- 7 - A 13 OR2 s 0 4 0 1 ~1644~3
- 8 - A 13 OR2 s 0 4 0 1 ~1644~4
- 1 - A 13 OR2 s 0 4 0 1 ~1650~1
- 4 - A 20 OR2 s 0 4 0 2 ~1650~2
- 2 - A 13 OR2 s 0 4 0 2 ~1650~3
- 8 - A 18 OR2 s 0 4 0 1 ~1650~4
- 6 - A 18 DFFE + 0 4 1 8 :1657
- 4 - A 13 DFFE + 0 4 1 8 :1658
- 3 - A 18 DFFE + 0 4 1 8 :1659
- 6 - A 24 AND2 s 0 2 0 3 ~1922~1
- 3 - A 23 OR2 s 0 4 0 1 ~1922~2
- 4 - A 23 OR2 s 0 4 0 2 ~1922~3
- 7 - A 21 OR2 s 0 4 0 1 ~1928~1
- 6 - A 21 OR2 s 0 4 0 2 ~1928~2
- 6 - A 22 OR2 s 0 4 0 1 ~1934~1
- 1 - A 22 OR2 s 0 4 0 1 ~1934~2
- 4 - A 18 OR2 s 0 3 0 1 ~1934~3
- 4 - A 24 OR2 s 0 4 0 1 ~1934~4
- 5 - A 24 OR2 s 0 4 0 2 ~1934~5
- 3 - A 24 DFFE + 0 4 1 7 :1941
- 2 - A 24 DFFE + 0 4 1 7 :1942
- 8 - A 24 DFFE + 0 3 1 7 :1943
- 1 - B 13 AND2 s ! 0 4 0 5 ~1956~1
- 5 - B 16 OR2 ! 0 4 0 3 :1956
- 6 - B 16 AND2 0 4 0 5 :1983
- 8 - B 16 OR2 ! 0 4 0 6 :2010
- 4 - B 16 AND2 0 4 0 3 :2037
- 5 - B 13 AND2 0 4 0 6 :2064
- 3 - B 16 AND2 s ! 0 4 0 6 ~2091~1
- 3 - B 13 OR2 ! 0 4 0 2 :2091
- 4 - B 13 AND2 0 4 0 9 :2118
- 2 - B 13 OR2 ! 0 4 0 3 :2145
- 7 - B 13 AND2 0 4 0 6 :2172
- 2 - B 16 OR2 s 0 4 0 1 ~2199~1
- 6 - B 13 OR2 ! 0 4 0 5 :2199
- 8 - B 15 OR2 s ! 0 2 0 3 ~2262~1
- 1 - B 18 AND2 s ! 0 2 0 1 ~2279~1
- 2 - B 18 AND2 s 0 4 0 1 ~2279~2
- 8 - B 13 AND2 s 0 4 0 1 ~2279~3
- 8 - B 18 OR2 s 0 4 0 6 ~2279~4
- 1 - B 24 OR2 s 0 2 0 1 ~2280~1
- 2 - B 20 AND2 s ! 0 2 0 3 ~2281~1
- 4 - B 19 OR2 s 0 2 0 3 ~2284~1
- 5 - B 19 OR2 s 0 2 0 6 ~2285~1
- 5 - B 18 AND2 s ! 0 2 0 3 ~2288~1
- 3 - B 21 OR2 s 0 4 0 1 ~2289~1
- 7 - B 16 DFFE + 0 4 0 1 origin13 (:2292)
- 2 - B 19 DFFE + 0 4 0 1 origin12 (:2293)
- 6 - B 14 DFFE + 0 4 0 1 origin11 (:2294)
- 3 - B 18 DFFE + 0 4 0 1 origin10 (:2295)
- 5 - B 23 DFFE + 0 4 0 1 origin9 (:2296)
- 3 - B 23 DFFE + 0 4 0 1 origin8 (:2297)
- 4 - B 18 DFFE + 0 4 0 1 origin7 (:2298)
- 6 - B 21 DFFE + 0 4 0 1 origin6 (:2299)
- 4 - B 21 DFFE + 0 3 0 1 origin5 (:2300)
- 7 - B 17 DFFE + 0 4 0 1 origin4 (:2301)
- 5 - B 17 DFFE + 0 4 0 1 origin3 (:2302)
- 1 - B 21 DFFE + 0 4 0 1 origin2 (:2303)
- 1 - B 14 DFFE + 0 4 0 1 origin1 (:2304)
- 4 - B 14 DFFE + 0 4 0 1 origin0 (:2305)
- 7 - B 19 DFFE + 0 3 0 1 divider13 (:2349)
- 3 - B 19 DFFE + 0 3 0 1 divider12 (:2350)
- 7 - B 14 DFFE + 0 3 0 1 divider11 (:2351)
- 7 - B 23 DFFE + 0 3 0 1 divider10 (:2352)
- 6 - B 23 DFFE + 0 3 0 1 divider9 (:2353)
- 4 - B 23 DFFE + 0 3 0 1 divider8 (:2354)
- 7 - B 18 DFFE + 0 3 0 1 divider7 (:2355)
- 7 - B 21 DFFE + 0 3 0 1 divider6 (:2356)
- 5 - B 21 DFFE + 0 3 0 1 divider5 (:2357)
- 8 - B 17 DFFE + 0 3 0 1 divider4 (:2358)
- 6 - B 17 DFFE + 0 3 0 1 divider3 (:2359)
- 4 - B 17 DFFE + 0 3 0 1 divider2 (:2360)
- 3 - B 14 DFFE + 0 3 0 1 divider1 (:2361)
- 5 - B 14 DFFE + 0 2 0 2 divider0 (:2362)
- 4 - B 07 DFFE 0 1 1 0 :2383
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_try.rpt
musicpro_try
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 32/ 48( 66%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 11/ 96( 11%) 1/ 48( 2%) 33/ 48( 68%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_try.rpt
musicpro_try
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 29 clk_4
LCELL 16 :18
INPUT 14 clk_6M
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_try.rpt
musicpro_try
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 clr
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_try.rpt
musicpro_try
** EQUATIONS **
clk_4 : INPUT;
clk_6M : INPUT;
clr : INPUT;
-- Node name is 'carry'
-- Equation name is 'carry', type is output
carry = _LC6_B19;
-- Node name is ':43' = 'counter0'
-- Equation name is 'counter0', location is LC1_A18, type is buried.
counter0 = DFFE( _LC5_A18, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
-- Node name is '~42~1' = 'counter1~1'
-- Equation name is '~42~1', location is LC5_A23, type is buried.
-- synthesized logic cell
_LC5_A23 = LCELL( _EQ001);
_EQ001 = !counter1 & counter2 & _LC2_A23 & _LC7_A18;
-- Node name is ':42' = 'counter1'
-- Equation name is 'counter1', location is LC5_A20, type is buried.
counter1 = DFFE( _LC2_A20, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
-- Node name is '~41~1' = 'counter2~1'
-- Equation name is '~41~1', location is LC8_A20, type is buried.
-- synthesized logic cell
_LC8_A20 = LCELL( _EQ002);
_EQ002 = counter0 & !counter1 & _LC1_A15 & _LC1_A23;
-- Node name is ':41' = 'counter2'
-- Equation name is 'counter2', location is LC2_A21, type is buried.
counter2 = DFFE( _EQ003, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
_EQ003 = counter2 & !_LC3_A20 & !_LC4_A22
# !counter2 & _LC3_A20 & !_LC4_A22;
-- Node name is ':40' = 'counter3'
-- Equation name is 'counter3', location is LC7_A23, type is buried.
counter3 = DFFE( _EQ004, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
_EQ004 = counter3 & !_LC4_A22 & !_LC6_A23
# !counter3 & !_LC4_A22 & _LC6_A23;
-- Node name is ':39' = 'counter4'
-- Equation name is 'counter4', location is LC8_A22, type is buried.
counter4 = DFFE( _EQ005, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
_EQ005 = counter4 & !_LC4_A22 & !_LC8_A23
# !counter4 & !_LC4_A22 & _LC8_A23;
-- Node name is ':38' = 'counter5'
-- Equation name is 'counter5', location is LC2_A22, type is buried.
counter5 = DFFE( _EQ006, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
_EQ006 = !counter4 & counter5 & !_LC4_A22
# counter5 & !_LC4_A22 & !_LC8_A23
# counter4 & !counter5 & !_LC4_A22 & _LC8_A23;
-- Node name is ':37' = 'counter6'
-- Equation name is 'counter6', location is LC3_A17, type is buried.
counter6 = DFFE( _EQ007, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
_EQ007 = counter6 & !_LC1_A17 & !_LC4_A22
# !counter6 & _LC1_A17 & !_LC4_A22;
-- Node name is ':36' = 'counter7'
-- Equation name is 'counter7', location is LC4_A17, type is buried.
counter7 = DFFE( _EQ008, GLOBAL( clk_4), GLOBAL(!clr), VCC, VCC);
_EQ008 = !counter6 & counter7 & !_LC4_A22
# counter7 & !_LC1_A17 & !_LC4_A22
# counter6 & !counter7 & _LC1_A17 & !_LC4_A22;
-- Node name is ':2362' = 'divider0'
-- Equation name is 'divider0', location is LC5_B14, type is buried.
divider0 = DFFE( _EQ009, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ009 = !divider0
# _LC6_B19 & origin0;
-- Node name is ':2361' = 'divider1'
-- Equation name is 'divider1', location is LC3_B14, type is buried.
divider1 = DFFE( _EQ010, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ010 = divider0 & !divider1 & !_LC6_B19
# !divider0 & divider1 & !_LC6_B19
# _LC6_B19 & origin1;
-- Node name is ':2360' = 'divider2'
-- Equation name is 'divider2', location is LC4_B17, type is buried.
divider2 = DFFE( _EQ011, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ011 = _LC6_B19 & origin2
# divider2 & !_LC2_B14 & !_LC6_B19
# !divider2 & _LC2_B14 & !_LC6_B19;
-- Node name is ':2359' = 'divider3'
-- Equation name is 'divider3', location is LC6_B17, type is buried.
divider3 = DFFE( _EQ012, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ012 = _LC6_B19 & origin3
# divider3 & !_LC1_B17 & !_LC6_B19
# !divider3 & _LC1_B17 & !_LC6_B19;
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