musicprots.v

采用Verilog HDL设计

//对musicpro.v的测试文件
//add the cycle of clk,decrease the time simulating
`timescale 10ns/1ns
//`define hclk_cyc 83   //6Mhz
`define clk_cyc 5   //4hz
module musicprots;//(clk_6M,clk_4,speaker,high,mid,low)//,carry);
reg clk_6M,clk_4;
wire speaker,carry;
wire[3:0]high,mid,low;
initial
  begin
    clk_6M<=0;
    clk_4<=0;
    #450000000 $stop;
  end
always 
  begin
     # 10   clk_6M<=~clk_6M;
    
    # `clk_cyc  clk_6M<=~clk_6M;
   
  end
always 
  begin
    # 24999995 clk_4<=~clk_4;
    # `clk_cyc  clk_4<=~clk_4;
    
    
    
  end
  
  musicpro musicpro(clk_6M,clk_4,speaker,high,mid,low,carry);
endmodule