clk_pro_ts.v

采用Verilog HDL设计

//add the cycle of clk,decrease the time simulating
`timescale 1ns/100ps
`define hclk_cyc 25   //20Mhz
//`define hclk_cyc 250  //2Mhz
`define one-ms 000000
module clk_pro_ts;
  reg clk,rst;
  wire clk_6M,clk_4;
  
  always #`hclk_cyc  clk=~clk;
  
  initial
    begin
     clk=0;
      rst=0;
      #10 rst=1;
      #500 rst=0;
    #520000000 $stop;
     end
//use for simple test
//defparam
//  clk_pro.bas_cnt_M=20000-1,
//  clk_pro.bas_cnt_W=14;//2^15=32768
clkpro clkpro(clk,clk_6M,clk_4);
endmodule