📄 musicpro_top.rpt
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Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_top.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/14/2004 23:02:19
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
musicpro_top
EPF10K10LC84-3 3 22 0 0 0 % 218 37 %
User Pins: 3 22 0
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_top.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Flipflop '|musicpro_try:19|:1940' stuck at GND
Warning: Flipflop '|musicpro_try:19|:1656' stuck at GND
Warning: Flipflop '|musicpro_try:19|:1372' stuck at GND
Warning: Flipflop '|musicpro_try:19|:1373' stuck at GND
Warning: Flipflop '|musicpro_try:19|:1374' stuck at GND
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_top.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
musicpro_top@1 clk
musicpro_top@84 clr
musicpro_top@23 high0
musicpro_top@22 high1
musicpro_top@21 high2
musicpro_top@19 high3
musicpro_top@18 high4
musicpro_top@17 high5
musicpro_top@16 high6
musicpro_top@62 low0
musicpro_top@61 low1
musicpro_top@60 low2
musicpro_top@59 low3
musicpro_top@58 low4
musicpro_top@54 low5
musicpro_top@53 low6
musicpro_top@36 mid0
musicpro_top@35 mid1
musicpro_top@30 mid2
musicpro_top@29 mid3
musicpro_top@28 mid4
musicpro_top@27 mid5
musicpro_top@25 mid6
musicpro_top@52 speaker
musicpro_top@44 startstop
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_top.rpt
** FILE HIERARCHY **
|p7segment:5|
|p7segment:4|
|p7segment:3|
|clkdiv:18|
|clkdiv:18|lpm_add_sub:130|
|clkdiv:18|lpm_add_sub:130|addcore:adder|
|clkdiv:18|lpm_add_sub:130|altshift:result_ext_latency_ffs|
|clkdiv:18|lpm_add_sub:130|altshift:carry_ext_latency_ffs|
|clkdiv:18|lpm_add_sub:130|altshift:oflow_ext_latency_ffs|
|clkdiv:18|lpm_add_sub:131|
|clkdiv:18|lpm_add_sub:131|addcore:adder|
|clkdiv:18|lpm_add_sub:131|altshift:result_ext_latency_ffs|
|clkdiv:18|lpm_add_sub:131|altshift:carry_ext_latency_ffs|
|clkdiv:18|lpm_add_sub:131|altshift:oflow_ext_latency_ffs|
|musicpro_try:19|
|musicpro_try:19|lpm_add_sub:2384|
|musicpro_try:19|lpm_add_sub:2384|addcore:adder|
|musicpro_try:19|lpm_add_sub:2384|altshift:result_ext_latency_ffs|
|musicpro_try:19|lpm_add_sub:2384|altshift:carry_ext_latency_ffs|
|musicpro_try:19|lpm_add_sub:2384|altshift:oflow_ext_latency_ffs|
|musicpro_try:19|lpm_add_sub:2385|
|musicpro_try:19|lpm_add_sub:2385|addcore:adder|
|musicpro_try:19|lpm_add_sub:2385|altshift:result_ext_latency_ffs|
|musicpro_try:19|lpm_add_sub:2385|altshift:carry_ext_latency_ffs|
|musicpro_try:19|lpm_add_sub:2385|altshift:oflow_ext_latency_ffs|
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_top.rpt
musicpro_top
***** Logic for device 'musicpro_top' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R R R R R R R O
E E E E E E E E E E E E E N
S S S S S S S V S G S G S S S S F
E E E E E E E C E N E N E E E E _ ^
R R R R R R R C R D R D R R R R # D n
V V V V V V V I V I c c V I V V V V T O C
E E E E E E E N E N l l E N E E E E C N E
D D D D D D D T D T k r D T D D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | RESERVED
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
high6 | 16 70 | RESERVED
high5 | 17 69 | RESERVED
high4 | 18 68 | GNDINT
high3 | 19 67 | RESERVED
VCCINT | 20 66 | RESERVED
high2 | 21 65 | RESERVED
high1 | 22 EPF10K10LC84-3 64 | RESERVED
high0 | 23 63 | VCCINT
RESERVED | 24 62 | low0
mid6 | 25 61 | low1
GNDINT | 26 60 | low2
mid5 | 27 59 | low3
mid4 | 28 58 | low4
mid3 | 29 57 | #TMS
mid2 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | low5
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ m m R R R V G G G s V G R R R R R s l
C n i i E E E C N N N t C N E E E E E p o
C C d d S S S C D D D a C D S S S S S e w
I O 1 0 E E E I I I I r I I E E E E E a 6
N N R R R N N N N t N N R R R R R k
T F V V V T T T T s T T V V V V V e
I E E E t E E E E E r
G D D D o D D D D D
p
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro_top.rpt
musicpro_top
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 4/22( 18%)
A14 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 5/22( 22%)
A16 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
A18 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 1/2 3/22( 13%)
A19 7/ 8( 87%) 3/ 8( 37%) 1/ 8( 12%) 2/2 1/2 3/22( 13%)
A22 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 4/22( 18%)
A23 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
B4 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 12/22( 54%)
B14 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 1/2 4/22( 18%)
B15 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 1/2 13/22( 59%)
B16 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 10/22( 45%)
B17 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 8/22( 36%)
B18 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 16/22( 72%)
B19 7/ 8( 87%) 3/ 8( 37%) 0/ 8( 0%) 1/2 1/2 12/22( 54%)
B21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%)
B22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
B23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
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