song.v

采用Verilog HDL设计

/* 乐曲演奏电路子模块，非阻塞赋值
   几乎完全同书                     */
module song(clk_6M,clk_4,speaker,high,mid,low,carry);
  input  clk_6M,clk_4;		//clk_6M: 用于产生各种音阶频率的基准频率；clk_4:  用于控制音长（节拍）的时钟频率
  output speaker,carry;		//speaker：用于激励扬声器的输出信号，为方波；carry：计数器divider的进位输出
  output [3:0]high,mid,low;	//分别用于显示高音、中音和低音音符，各用一个数码管来显示
  reg[3:0]high,mid,low;
  reg[13:0]divider,origin;	//divider :对clk_6M进行分频的计数器；origin:各种音阶频率对应的预置数 
  reg[7:0]counter;			//用于控制每个音符的时长及演奏的循环进行 
  reg speaker;
  wire carry;
  
/* （1）反馈预置计数器 */    
  assign carry=(divider==16383);
  always @(posedge clk_6M )
    begin      
        if(divider==16383)
			divider<=origin;
		else
            divider<=divider+1;   
    end

/* （2）2分频器 */  
  always @(posedge carry)
    speaker<=~speaker;  	         //half frequency division

/* （3）乐谱产生电路 */
 always@(posedge clk_4)        //同书上
    case({high,mid,low})             //preset the origin value for cnt according the note
      12'h003:origin<=7281;
      12'h005:origin<=8730;
      12'h006:origin<=9565;
      12'h007:origin<=10310;
      12'h010:origin<=10647;
      12'h020:origin<=11272;
      12'h030:origin<=11831;
      12'h050:origin<=12556;
      12'h060:origin<=12974;
      12'h100:origin<=13516;
      12'h000:origin<=16383;
      default:origin<=16383;
    endcase
    
/* （4）音名显示 */  
  always@(posedge clk_4)
    begin
      if(counter==47)
        counter<=0;                  //time for loop play
      else  
		counter<=counter+1;

      case(counter)                  // 记谱
          0: {high,mid,low}<=12'h003;//low 3，并持续4个节拍
          1: {high,mid,low}<=12'h003;
          2: {high,mid,low}<=12'h003;
          3: {high,mid,low}<=12'h003;
          4: {high,mid,low}<=12'h005;//low 5
          5: {high,mid,low}<=12'h005;
          6: {high,mid,low}<=12'h005;
          7: {high,mid,low}<=12'h006;//low6
          8: {high,mid,low}<=12'h010;//mid 1
          9: {high,mid,low}<=12'h010;
          10:{high,mid,low}<=12'h010;
          11:{high,mid,low}<=12'h020;//mid 2
          12:{high,mid,low}<=12'h006;//low 6
          13:{high,mid,low}<=12'h010;//mid 1
          14:{high,mid,low}<=12'h005;//low 5
          15:{high,mid,low}<=12'h005;
          16:{high,mid,low}<=12'h050;//mid 5
          17:{high,mid,low}<=12'h050;
          18:{high,mid,low}<=12'h050;
          19:{high,mid,low}<=12'h100;//hig 1
          20:{high,mid,low}<=12'h060;//mid 6
          21:{high,mid,low}<=12'h050;//mid 5
          22:{high,mid,low}<=12'h030;//mid 3
          23:{high,mid,low}<=12'h050;//mid 5
          24:{high,mid,low}<=12'h020;//mid 2
          25:{high,mid,low}<=12'h020;
          26:{high,mid,low}<=12'h020;
          27:{high,mid,low}<=12'h020;
          28:{high,mid,low}<=12'h020;
          29:{high,mid,low}<=12'h020;
          30:{high,mid,low}<=12'h020;
          31:{high,mid,low}<=12'h020;
          32:{high,mid,low}<=12'h020;
          33:{high,mid,low}<=12'h020;
          34:{high,mid,low}<=12'h020;
          35:{high,mid,low}<=12'h030;//mid 3
          36:{high,mid,low}<=12'h007;//low 7
          37:{high,mid,low}<=12'h007;
          38:{high,mid,low}<=12'h006;//low 6
          39:{high,mid,low}<=12'h006;
          40:{high,mid,low}<=12'h005;//low 5
          41:{high,mid,low}<=12'h005;
          42:{high,mid,low}<=12'h005;
          43:{high,mid,low}<=12'h006;//low 6
          44:{high,mid,low}<=12'h010;//mid 1
          45:{high,mid,low}<=12'h010;
          46:{high,mid,low}<=12'h020;//mid 2
          47:{high,mid,low}<=12'h020;
          //…………………………
      endcase
    end
endmodule