musicpro.rpt

采用Verilog HDL设计

-- Node name is '~1895~2' 
-- Equation name is '~1895~2', location is LC8_B18, type is buried.
-- synthesized logic cell 
!_LC8_B18 = _LC8_B18~NOT;
_LC8_B18~NOT = LCELL( _EQ101);
  _EQ101 =  _LC3_B18 & !_LC6_B18;

-- Node name is '~1895~3' 
-- Equation name is '~1895~3', location is LC6_C20, type is buried.
-- synthesized logic cell 
!_LC6_C20 = _LC6_C20~NOT;
_LC6_C20~NOT = LCELL( _EQ102);
  _EQ102 = !_LC1_C20 & !_LC4_C20 & !_LC5_B19;

-- Node name is '~1895~4' 
-- Equation name is '~1895~4', location is LC8_C18, type is buried.
-- synthesized logic cell 
!_LC8_C18 = _LC8_C18~NOT;
_LC8_C18~NOT = LCELL( _EQ103);
  _EQ103 = !_LC4_B18 & !_LC6_C20 & !_LC8_B18;

-- Node name is ':1895' 
-- Equation name is '_LC5_C18', type is buried 
!_LC5_C18 = _LC5_C18~NOT;
_LC5_C18~NOT = LCELL( _EQ104);
  _EQ104 =  _LC3_B15
         # !_LC8_B15
         # !_LC7_B15
         #  _LC8_C18;

-- Node name is ':1922' 
-- Equation name is '_LC6_C18', type is buried 
_LC6_C18 = LCELL( _EQ105);
  _EQ105 =  _LC3_B15 &  _LC7_B15 & !_LC8_B15 & !_LC8_C18;

-- Node name is ':1949' 
-- Equation name is '_LC2_C18', type is buried 
!_LC2_C18 = _LC2_C18~NOT;
_LC2_C18~NOT = LCELL( _EQ106);
  _EQ106 =  _LC7_B15
         # !_LC8_B15
         # !_LC3_B15
         #  _LC8_C18;

-- Node name is ':1976' 
-- Equation name is '_LC4_C18', type is buried 
_LC4_C18 = LCELL( _EQ107);
  _EQ107 =  _LC3_B15 &  _LC7_B15 &  _LC8_B15 & !_LC8_C18;

-- Node name is ':2003' 
-- Equation name is '_LC7_C20', type is buried 
_LC7_C20 = LCELL( _EQ108);
  _EQ108 =  _LC1_C20 &  _LC3_C18 & !_LC4_C20 & !_LC5_B19;

-- Node name is ':2030' 
-- Equation name is '_LC5_C20', type is buried 
!_LC5_C20 = _LC5_C20~NOT;
_LC5_C20~NOT = LCELL( _EQ109);
  _EQ109 =  _LC4_C20
         # !_LC3_C18
         # !_LC5_B19
         #  _LC1_C20;

-- Node name is ':2057' 
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = LCELL( _EQ110);
  _EQ110 =  _LC1_C20 &  _LC3_C18 & !_LC4_C20 &  _LC5_B19;

-- Node name is ':2084' 
-- Equation name is '_LC2_C20', type is buried 
!_LC2_C20 = _LC2_C20~NOT;
_LC2_C20~NOT = LCELL( _EQ111);
  _EQ111 = !_LC4_C20
         # !_LC3_C18
         #  _LC5_B19
         # !_LC1_C20;

-- Node name is ':2111' 
-- Equation name is '_LC8_C20', type is buried 
_LC8_C20 = LCELL( _EQ112);
  _EQ112 = !_LC1_C20 &  _LC3_C18 &  _LC4_C20 &  _LC5_B19;

-- Node name is ':2138' 
-- Equation name is '_LC1_C18', type is buried 
!_LC1_C18 = _LC1_C18~NOT;
_LC1_C18~NOT = LCELL( _EQ113);
  _EQ113 = !_LC4_B18
         #  _LC8_B18
         # !_LC7_C18
         #  _LC6_C20;

-- Node name is '~2165~1' 
-- Equation name is '~2165~1', location is LC7_C18, type is buried.
-- synthesized logic cell 
_LC7_C18 = LCELL( _EQ114);
  _EQ114 = !_LC3_B15 & !_LC7_B15 & !_LC8_B15;

-- Node name is '~2165~2' 
-- Equation name is '~2165~2', location is LC3_C18, type is buried.
-- synthesized logic cell 
_LC3_C18 = LCELL( _EQ115);
  _EQ115 = !_LC4_B18 &  _LC7_C18 & !_LC8_B18;

-- Node name is '~2201~1' 
-- Equation name is '~2201~1', location is LC1_C22, type is buried.
-- synthesized logic cell 
!_LC1_C22 = _LC1_C22~NOT;
_LC1_C22~NOT = LCELL( _EQ116);
  _EQ116 =  _LC7_C20
         #  _LC4_C18;

-- Node name is '~2218~1' 
-- Equation name is '~2218~1', location is LC7_C21, type is buried.
-- synthesized logic cell 
!_LC7_C21 = _LC7_C21~NOT;
_LC7_C21~NOT = LCELL( _EQ117);
  _EQ117 = !_LC1_C18 & !_LC2_C20 & !_LC8_C20;

-- Node name is '~2218~2' 
-- Equation name is '~2218~2', location is LC8_C21, type is buried.
-- synthesized logic cell 
_LC8_C21 = LCELL( _EQ118);
  _EQ118 = !_LC3_C20 & !_LC5_C18 & !_LC6_C18 & !_LC7_C21;

-- Node name is '~2218~3' 
-- Equation name is '~2218~3', location is LC1_C19, type is buried.
-- synthesized logic cell 
_LC1_C19 = LCELL( _EQ119);
  _EQ119 =  _LC3_C18 & !_LC6_C20;

-- Node name is '~2218~4' 
-- Equation name is '~2218~4', location is LC6_C21, type is buried.
-- synthesized logic cell 
_LC6_C21 = LCELL( _EQ120);
  _EQ120 =  _LC1_C22 & !_LC6_C15 &  _LC8_C21
         #  _LC1_C19;

-- Node name is ':2218' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = LCELL( _EQ121);
  _EQ121 =  _LC2_C20
         #  _LC1_C18
         #  _LC8_C20
         #  _LC2_C21;

-- Node name is ':2219' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ122);
  _EQ122 =  _LC2_C21
         #  _LC3_C20
         # !_LC1_C22
         #  _LC5_C20;

-- Node name is '~2220~1' 
-- Equation name is '~2220~1', location is LC6_C15, type is buried.
-- synthesized logic cell 
!_LC6_C15 = _LC6_C15~NOT;
_LC6_C15~NOT = LCELL( _EQ123);
  _EQ123 = !_LC2_C18 & !_LC5_C20;

-- Node name is ':2220' 
-- Equation name is '_LC7_C23', type is buried 
_LC7_C23 = LCELL( _EQ124);
  _EQ124 =  _LC2_C21
         #  _LC3_C20
         #  _LC1_C18
         #  _LC6_C15;

-- Node name is ':2221' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ125);
  _EQ125 =  _LC6_C21
         #  _LC8_C20
         #  _LC6_C18
         #  _LC3_C20;

-- Node name is ':2222' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ126);
  _EQ126 =  _LC7_C20
         #  _LC2_C18
         #  _LC6_C21
         #  _LC2_C20;

-- Node name is ':2223' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = LCELL( _EQ127);
  _EQ127 =  _LC6_C21
         #  _LC8_C20
         #  _LC7_C20
         #  _LC1_C18;

-- Node name is '~2224~1' 
-- Equation name is '~2224~1', location is LC2_C21, type is buried.
-- synthesized logic cell 
_LC2_C21 = LCELL( _EQ128);
  _EQ128 =  _LC6_C21
         #  _LC5_C18;

-- Node name is '~2224~2' 
-- Equation name is '~2224~2', location is LC6_C14, type is buried.
-- synthesized logic cell 
_LC6_C14 = LCELL( _EQ129);
  _EQ129 =  _LC4_C18
         #  _LC2_C18;

-- Node name is ':2224' 
-- Equation name is '_LC3_C16', type is buried 
_LC3_C16 = LCELL( _EQ130);
  _EQ130 =  _LC4_C18
         #  _LC2_C18
         #  _LC1_C18
         #  _LC2_C21;

-- Node name is ':2225' 
-- Equation name is '_LC7_C24', type is buried 
_LC7_C24 = LCELL( _EQ131);
  _EQ131 =  _LC2_C21
         #  _LC3_C20
         #  _LC8_C20;

-- Node name is ':2226' 
-- Equation name is '_LC5_C24', type is buried 
_LC5_C24 = LCELL( _EQ132);
  _EQ132 =  _LC4_C21
         #  _LC6_C18;

-- Node name is '~2227~1' 
-- Equation name is '~2227~1', location is LC5_C23, type is buried.
-- synthesized logic cell 
_LC5_C23 = LCELL( _EQ133);
  _EQ133 =  _LC6_C21
         #  _LC8_C20
         #  _LC6_C18;

-- Node name is ':2227' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = LCELL( _EQ134);
  _EQ134 =  _LC5_C23
         #  _LC2_C20
         #  _LC1_C18
         #  _LC6_C15;

-- Node name is ':2228' 
-- Equation name is '_LC7_C14', type is buried 
_LC7_C14 = LCELL( _EQ135);
  _EQ135 =  _LC3_C21
         #  _LC6_C14
         #  _LC2_C20
         #  _LC3_C20;

-- Node name is ':2229' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = LCELL( _EQ136);
  _EQ136 =  _LC3_C23
         # !_LC1_C22;

-- Node name is ':2230' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ137);
  _EQ137 =  _LC2_C21
         #  _LC3_C20
         #  _LC7_C20
         #  _LC2_C18;

-- Node name is ':2309' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = DFFE(!_LC5_C16,  _LC5_C15,  VCC,  VCC,  VCC);



Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Aut