📄 musicpro.rpt
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- 1 - B 24 AND2 s ! 0 2 0 4 ~71~1
- 4 - B 21 OR2 s 0 3 0 1 ~96~1
- 3 - B 23 AND2 s ! 0 2 0 5 ~146~1
- 6 - B 24 OR2 s 0 2 0 3 ~146~2
- 5 - B 20 OR2 s 0 2 0 1 ~246~1
- 7 - B 23 OR2 s 0 4 0 1 ~271~1
- 1 - B 21 AND2 s ! 0 4 0 1 ~321~1
- 2 - B 22 OR2 ! 0 3 0 2 :546
- 3 - B 20 OR2 s ! 0 4 0 3 ~571~1
- 2 - B 14 OR2 s 0 4 0 4 ~571~2
- 4 - B 14 OR2 s 0 4 0 4 ~596~1
- 3 - B 14 OR2 s 0 4 0 4 ~621~1
- 2 - B 16 OR2 s 0 3 0 7 ~646~1
- 2 - B 23 AND2 s ! 0 4 0 3 ~1121~1
- 2 - B 20 OR2 s 0 3 0 2 ~1146~1
- 4 - B 15 OR2 s 0 3 0 1 ~1317~1
- 2 - B 24 OR2 s 0 3 0 1 ~1317~2
- 5 - B 15 AND2 s 0 4 0 1 ~1317~3
- 1 - B 15 AND2 ! 0 4 0 12 :1317
- 6 - B 18 DFFE + 0 1 1 1 :1347
- 7 - B 18 DFFE + 0 1 1 1 :1348
- 1 - B 18 DFFE + 0 1 1 1 :1349
- 4 - B 18 DFFE + 0 2 1 3 :1350
- 6 - B 14 OR2 s 0 3 0 1 ~1601~1
- 7 - B 14 OR2 s 0 4 0 1 ~1601~2
- 3 - B 22 OR2 s ! 0 4 0 1 ~1607~1
- 4 - B 22 OR2 s ! 0 4 0 1 ~1607~2
- 5 - B 22 OR2 s 0 4 0 1 ~1607~3
- 6 - B 22 OR2 s 0 4 0 1 ~1607~4
- 7 - B 22 OR2 s 0 4 0 1 ~1607~5
- 8 - B 22 OR2 s 0 4 0 1 ~1607~6
- 1 - B 22 AND2 s ! 0 4 0 2 ~1607~7
- 8 - B 21 OR2 s 0 4 0 4 ~1613~1
- 1 - B 14 AND2 s ! 0 3 0 3 ~1613~2
- 8 - B 14 OR2 s 0 4 0 1 ~1613~3
- 5 - B 21 OR2 s ! 0 3 0 1 ~1613~4
- 4 - B 24 OR2 s ! 0 4 0 2 ~1613~5
- 5 - B 24 AND2 s 0 1 0 1 ~1613~6
- 5 - B 14 OR2 s 0 2 0 1 ~1613~7
- 8 - B 24 OR2 s 0 4 0 1 ~1613~8
- 7 - B 24 OR2 s 0 4 0 1 ~1613~9
- 2 - B 18 DFFE + 0 1 1 1 :1619
- 4 - C 20 DFFE + 0 3 1 6 :1620
- 5 - B 19 DFFE + 0 2 1 6 :1621
- 1 - C 20 DFFE + 0 3 1 6 :1622
- 4 - B 20 OR2 s ! 0 4 0 1 ~1873~1
- 8 - B 23 OR2 s 0 4 0 1 ~1873~2
- 4 - B 23 OR2 s ! 0 4 0 3 ~1873~3
- 6 - B 21 OR2 s ! 0 4 0 1 ~1873~4
- 3 - B 21 OR2 s 0 2 0 2 ~1873~5
- 2 - B 21 OR2 s ! 0 4 0 1 ~1873~6
- 2 - B 15 OR2 s 0 4 0 3 ~1873~7
- 7 - B 21 AND2 s 0 3 0 4 ~1879~1
- 6 - B 15 OR2 s 0 4 0 1 ~1879~2
- 3 - B 24 OR2 s 0 4 0 2 ~1885~1
- 5 - B 18 DFFE + 0 1 1 1 :1891
- 3 - B 15 DFFE + 0 3 1 5 :1892
- 8 - B 15 DFFE + 0 3 1 5 :1893
- 7 - B 15 DFFE + 0 3 1 5 :1894
- 3 - B 18 AND2 s 0 4 0 1 ~1895~1
- 8 - B 18 AND2 s ! 0 2 0 3 ~1895~2
- 6 - C 20 AND2 s ! 0 3 0 3 ~1895~3
- 8 - C 18 AND2 s ! 0 3 0 4 ~1895~4
- 5 - C 18 OR2 ! 0 4 0 3 :1895
- 6 - C 18 AND2 0 4 0 4 :1922
- 2 - C 18 OR2 ! 0 4 0 5 :1949
- 4 - C 18 AND2 0 4 0 3 :1976
- 7 - C 20 AND2 0 4 0 4 :2003
- 5 - C 20 OR2 ! 0 4 0 2 :2030
- 3 - C 20 AND2 0 4 0 7 :2057
- 2 - C 20 OR2 ! 0 4 0 5 :2084
- 8 - C 20 AND2 0 4 0 6 :2111
- 1 - C 18 OR2 ! 0 4 0 6 :2138
- 7 - C 18 AND2 s 0 3 0 2 ~2165~1
- 3 - C 18 AND2 s 0 3 0 6 ~2165~2
- 1 - C 22 OR2 s ! 0 2 0 3 ~2201~1
- 7 - C 21 AND2 s ! 0 3 0 1 ~2218~1
- 8 - C 21 AND2 s 0 4 0 1 ~2218~2
- 1 - C 19 AND2 s 0 2 0 1 ~2218~3
- 6 - C 21 OR2 s 0 4 0 5 ~2218~4
- 5 - C 21 OR2 0 4 0 1 :2218
- 3 - C 15 OR2 0 4 0 1 :2219
- 6 - C 15 AND2 s ! 0 2 0 3 ~2220~1
- 7 - C 23 OR2 0 4 0 1 :2220
- 3 - C 23 OR2 0 4 0 2 :2221
- 1 - C 21 OR2 0 4 0 1 :2222
- 3 - C 21 OR2 0 4 0 2 :2223
- 2 - C 21 OR2 s 0 2 0 6 ~2224~1
- 6 - C 14 OR2 s 0 2 0 1 ~2224~2
- 3 - C 16 OR2 0 4 0 1 :2224
- 7 - C 24 OR2 0 3 0 1 :2225
- 5 - C 24 OR2 0 2 0 1 :2226
- 5 - C 23 OR2 s 0 3 0 1 ~2227~1
- 2 - C 23 OR2 0 4 0 1 :2227
- 7 - C 14 OR2 0 4 0 1 :2228
- 1 - C 14 OR2 0 2 0 1 :2229
- 4 - C 21 OR2 0 4 0 2 :2230
- 8 - C 15 DFFE + 0 3 0 1 divider13 (:2274)
- 7 - C 15 DFFE + 0 3 0 1 divider12 (:2275)
- 4 - C 15 DFFE + 0 3 0 1 divider11 (:2276)
- 8 - C 23 DFFE + 0 3 0 1 divider10 (:2277)
- 6 - C 23 DFFE + 0 3 0 1 divider9 (:2278)
- 7 - C 16 DFFE + 0 3 0 1 divider8 (:2279)
- 6 - C 16 DFFE + 0 3 0 1 divider7 (:2280)
- 4 - C 16 DFFE + 0 3 0 1 divider6 (:2281)
- 8 - C 24 DFFE + 0 3 0 1 divider5 (:2282)
- 6 - C 24 DFFE + 0 3 0 1 divider4 (:2283)
- 3 - C 24 DFFE + 0 3 0 1 divider3 (:2284)
- 8 - C 14 DFFE + 0 3 0 1 divider2 (:2285)
- 4 - C 14 DFFE + 0 3 0 1 divider1 (:2286)
- 5 - C 14 DFFE + 0 2 0 2 divider0 (:2287)
- 5 - C 16 DFFE 0 1 1 0 :2309
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro.rpt
musicpro
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 38/ 48( 79%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 11/ 96( 11%) 0/ 48( 0%) 31/ 48( 64%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro.rpt
musicpro
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 clk_4
LCELL 16 :17
INPUT 14 clk_6M
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\music\musicpro.rpt
musicpro
** EQUATIONS **
clk_4 : INPUT;
clk_6M : INPUT;
-- Node name is 'carry'
-- Equation name is 'carry', type is output
carry = _LC5_C15;
-- Node name is ':70' = 'counter0'
-- Equation name is 'counter0', location is LC1_B13, type is buried.
counter0 = DFFE(!counter0, GLOBAL( clk_4), VCC, VCC, VCC);
-- Node name is ':69' = 'counter1'
-- Equation name is 'counter1', location is LC6_B23, type is buried.
counter1 = DFFE( _EQ001, GLOBAL( clk_4), VCC, VCC, VCC);
_EQ001 = !counter0 & counter1 & _LC5_B23
# !counter0 & counter1 & !_LC1_B20
# counter0 & !counter1 & _LC5_B23
# counter0 & !counter1 & !_LC1_B20;
-- Node name is ':68' = 'counter2'
-- Equation name is 'counter2', location is LC7_B20, type is buried.
counter2 = DFFE( _EQ002, GLOBAL( clk_4), VCC, VCC, VCC);
_EQ002 = counter2 & !_LC1_B23 & _LC5_B23
# counter2 & !_LC1_B20 & !_LC1_B23
# !counter2 & _LC1_B23 & _LC5_B23
# !counter2 & !_LC1_B20 & _LC1_B23;
-- Node name is ':67' = 'counter3'
-- Equation name is 'counter3', location is LC6_B20, type is buried.
counter3 = DFFE( _EQ003, GLOBAL( clk_4), VCC, VCC, VCC);
_EQ003 = counter3 & _LC5_B23 & !_LC8_B20
# counter3 & !_LC1_B20 & !_LC8_B20
# !counter3 & _LC5_B23 & _LC8_B20
# !counter3 & !_LC1_B20 & _LC8_B20;
-- Node name is ':66' = 'counter4'
-- Equation name is 'counter4', location is LC3_B16, type is buried.
counter4 = DFFE( _EQ004, GLOBAL( clk_4), VCC, VCC, VCC);
_EQ004 = counter4 & !_LC1_B20
# !counter4 & _LC1_B20 & _LC5_B23;
-- Node name is ':65' = 'counter5'
-- Equation name is 'counter5', location is LC5_B16, type is buried.
counter5 = DFFE( _EQ005, GLOBAL( clk_4), VCC, VCC, VCC);
_EQ005 = counter5 & !_LC1_B20
# !counter4 & counter5 & _LC5_B23
# counter4 & !counter5 & _LC1_B20 & _LC5_B23;
-- Node name is ':64' = 'counter6'
-- Equation name is 'counter6', location is LC6_B16, type is buried.
counter6 = DFFE( _EQ006, GLOBAL( clk_4), VCC, VCC, VCC);
_EQ006 = counter6 & !_LC1_B16 & _LC5_B23
# !counter6 & _LC1_B16 & _LC5_B23
# counter6 & !_LC1_B16 & !_LC1_B20
# !counter6 & _LC1_B16 & !_LC1_B20;
-- Node name is ':63' = 'counter7'
-- Equation name is 'counter7', location is LC8_B16, type is buried.
counter7 = DFFE( _EQ007, GLOBAL( clk_4), VCC, VCC, VCC);
_EQ007 = !counter6 & counter7 & !_LC7_B16
# counter7 & !_LC1_B16 & !_LC7_B16
# counter6 & !counter7 & _LC1_B16 & !_LC7_B16;
-- Node name is ':2287' = 'divider0'
-- Equation name is 'divider0', location is LC5_C14, type is buried.
divider0 = DFFE( _EQ008, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ008 = !divider0
# _LC4_C21 & _LC5_C15;
-- Node name is ':2286' = 'divider1'
-- Equation name is 'divider1', location is LC4_C14, type is buried.
divider1 = DFFE( _EQ009, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ009 = _LC1_C14 & _LC5_C15
# divider0 & !divider1 & !_LC5_C15
# !divider0 & divider1 & !_LC5_C15;
-- Node name is ':2285' = 'divider2'
-- Equation name is 'divider2', location is LC8_C14, type is buried.
divider2 = DFFE( _EQ010, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ010 = _LC5_C15 & _LC7_C14
# divider2 & !_LC3_C14 & !_LC5_C15
# !divider2 & _LC3_C14 & !_LC5_C15;
-- Node name is ':2284' = 'divider3'
-- Equation name is 'divider3', location is LC3_C24, type is buried.
divider3 = DFFE( _EQ011, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ011 = _LC2_C23 & _LC5_C15
# divider3 & !_LC2_C14 & !_LC5_C15
# !divider3 & _LC2_C14 & !_LC5_C15;
-- Node name is ':2283' = 'divider4'
-- Equation name is 'divider4', location is LC6_C24, type is buried.
divider4 = DFFE( _EQ012, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ012 = _LC5_C15 & _LC5_C24
# divider4 & !_LC1_C24 & !_LC5_C15
# !divider4 & _LC1_C24 & !_LC5_C15;
-- Node name is ':2282' = 'divider5'
-- Equation name is 'divider5', location is LC8_C24, type is buried.
divider5 = DFFE( _EQ013, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ013 = _LC5_C15 & _LC7_C24
# divider5 & !_LC2_C24 & !_LC5_C15
# !divider5 & _LC2_C24 & !_LC5_C15;
-- Node name is ':2281' = 'divider6'
-- Equation name is 'divider6', location is LC4_C16, type is buried.
divider6 = DFFE( _EQ014, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ014 = _LC3_C16 & _LC5_C15
# divider6 & !_LC4_C24 & !_LC5_C15
# !divider6 & _LC4_C24 & !_LC5_C15;
-- Node name is ':2280' = 'divider7'
-- Equation name is 'divider7', location is LC6_C16, type is buried.
divider7 = DFFE( _EQ015, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ015 = _LC3_C21 & _LC5_C15
# divider7 & !_LC1_C16 & !_LC5_C15
# !divider7 & _LC1_C16 & !_LC5_C15;
-- Node name is ':2279' = 'divider8'
-- Equation name is 'divider8', location is LC7_C16, type is buried.
divider8 = DFFE( _EQ016, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ016 = _LC1_C21 & _LC5_C15
# divider8 & !_LC2_C16 & !_LC5_C15
# !divider8 & _LC2_C16 & !_LC5_C15;
-- Node name is ':2278' = 'divider9'
-- Equation name is 'divider9', location is LC6_C23, type is buried.
divider9 = DFFE( _EQ017, GLOBAL( clk_6M), VCC, VCC, VCC);
_EQ017 = _LC3_C23 & _LC5_C15
# divider9 & !_LC5_C15 & !_LC8_C16
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