decoder.rpt

采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理


Device-Specific Information:                           f:\vhdl\qdq\decoder.rpt
decoder

** EQUATIONS **

s1       : INPUT;
s2       : INPUT;
s3       : INPUT;
s4       : INPUT;
s5       : INPUT;
s6       : INPUT;
s7       : INPUT;
s8       : INPUT;

-- Node name is 'a' 
-- Equation name is 'a', type is output 
a        =  _LC4_B20;

-- Node name is 'b' 
-- Equation name is 'b', type is output 
b        =  _LC6_B14;

-- Node name is 'c' 
-- Equation name is 'c', type is output 
c        =  _LC2_B16;

-- Node name is 'd' 
-- Equation name is 'd', type is output 
d        =  _LC8_B20;

-- Node name is 'e' 
-- Equation name is 'e', type is output 
e        =  _LC3_B23;

-- Node name is 'f' 
-- Equation name is 'f', type is output 
f        =  _LC1_B16;

-- Node name is 'g' 
-- Equation name is 'g', type is output 
g        =  _LC8_B21;

-- Node name is 's1~1' 
-- Equation name is 's1~1', location is LC2_B20, type is buried.
-- synthesized logic cell 
_LC2_B20 = LCELL( _EQ001);
  _EQ001 =  _LC2_B23 & !s3 & !s5;

-- Node name is ':24' 
-- Equation name is '_LC7_B16', type is buried 
!_LC7_B16 = _LC7_B16~NOT;
_LC7_B16~NOT = LCELL( _EQ002);
  _EQ002 = !_LC3_B20
         #  s2
         # !s1;

-- Node name is ':96' 
-- Equation name is '_LC1_B20', type is buried 
!_LC1_B20 = _LC1_B20~NOT;
_LC1_B20~NOT = LCELL( _EQ003);
  _EQ003 =  _LC5_B16
         # !_LC5_B23
         # !s4;

-- Node name is '~120~1' 
-- Equation name is '~120~1', location is LC7_B23, type is buried.
-- synthesized logic cell 
_LC7_B23 = LCELL( _EQ004);
  _EQ004 =  s8
         #  s7
         #  s6
         # !s5;

-- Node name is '~144~1' 
-- Equation name is '~144~1', location is LC6_B23, type is buried.
-- synthesized logic cell 
_LC6_B23 = LCELL( _EQ005);
  _EQ005 =  _LC7_B20
         #  s8
         #  s7;

-- Node name is ':168' 
-- Equation name is '_LC1_B23', type is buried 
_LC1_B23 = LCELL( _EQ006);
  _EQ006 = !_LC7_B20 & !s6 &  s7 & !s8;

-- Node name is '~192~1' 
-- Equation name is '~192~1', location is LC5_B16, type is buried.
-- synthesized logic cell 
!_LC5_B16 = _LC5_B16~NOT;
_LC5_B16~NOT = LCELL( _EQ007);
  _EQ007 = !s1 & !s2 & !s3;

-- Node name is '~192~2' 
-- Equation name is '~192~2', location is LC7_B20, type is buried.
-- synthesized logic cell 
!_LC7_B20 = _LC7_B20~NOT;
_LC7_B20~NOT = LCELL( _EQ008);
  _EQ008 = !_LC5_B16 & !s4 & !s5;

-- Node name is '~192~3' 
-- Equation name is '~192~3', location is LC6_B20, type is buried.
-- synthesized logic cell 
_LC6_B20 = LCELL( _EQ009);
  _EQ009 =  _LC5_B16
         #  s4;

-- Node name is '~216~1' 
-- Equation name is '~216~1', location is LC5_B23, type is buried.
-- synthesized logic cell 
!_LC5_B23 = _LC5_B23~NOT;
_LC5_B23~NOT = LCELL( _EQ010);
  _EQ010 =  s8
         #  s7
         #  s6
         #  s5;

-- Node name is '~216~2' 
-- Equation name is '~216~2', location is LC3_B20, type is buried.
-- synthesized logic cell 
!_LC3_B20 = _LC3_B20~NOT;
_LC3_B20~NOT = LCELL( _EQ011);
  _EQ011 = !_LC5_B23
         #  s4
         #  s3;

-- Node name is '~216~3' 
-- Equation name is '~216~3', location is LC5_B20, type is buried.
-- synthesized logic cell 
!_LC5_B20 = _LC5_B20~NOT;
_LC5_B20~NOT = LCELL( _EQ012);
  _EQ012 = !_LC5_B23
         #  s4;

-- Node name is ':248' 
-- Equation name is '_LC4_B20', type is buried 
_LC4_B20 = LCELL( _EQ013);
  _EQ013 = !_LC5_B16 &  _LC5_B23 &  s4
         #  _LC3_B16;

-- Node name is '~249~1' 
-- Equation name is '~249~1', location is LC4_B23, type is buried.
-- synthesized logic cell 
!_LC4_B23 = _LC4_B23~NOT;
_LC4_B23~NOT = LCELL( _EQ014);
  _EQ014 =  _LC6_B20 &  _LC6_B23
         #  _LC6_B23 &  _LC7_B23
         #  _LC6_B20 & !s6
         #  _LC7_B23 & !s6;

-- Node name is ':249' 
-- Equation name is '_LC6_B14', type is buried 
_LC6_B14 = LCELL( _EQ015);
  _EQ015 =  _LC4_B16
         #  _LC4_B23;

-- Node name is '~250~1' 
-- Equation name is '~250~1', location is LC2_B14, type is buried.
-- synthesized logic cell 
_LC2_B14 = LCELL( _EQ016);
  _EQ016 = !_LC1_B20 & !_LC4_B23 &  s2
         # !_LC1_B20 & !_LC2_B20 & !_LC4_B23;

-- Node name is '~250~2' 
-- Equation name is '~250~2', location is LC8_B16, type is buried.
-- synthesized logic cell 
_LC8_B16 = LCELL( _EQ017);
  _EQ017 = !_LC1_B23 &  _LC2_B14 & !_LC6_B16 & !_LC7_B16;

-- Node name is '~250~3' 
-- Equation name is '~250~3', location is LC4_B16, type is buried.
-- synthesized logic cell 
_LC4_B16 = LCELL( _EQ018);
  _EQ018 =  _LC8_B16
         #  _LC2_B20 & !s2 & !s8;

-- Node name is ':250' 
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = LCELL( _EQ019);
  _EQ019 =  _LC2_B20 &  s2 & !s8
         #  _LC4_B16;

-- Node name is ':251' 
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = LCELL( _EQ020);
  _EQ020 = !_LC5_B16 &  _LC5_B23 &  s4
         #  _LC8_B21;

-- Node name is '~252~1' 
-- Equation name is '~252~1', location is LC2_B23, type is buried.
-- synthesized logic cell 
_LC2_B23 = LCELL( _EQ021);
  _EQ021 = !s1 & !s4 & !s6 & !s7;

-- Node name is '~252~2' 
-- Equation name is '~252~2', location is LC8_B23, type is buried.
-- synthesized logic cell 
_LC8_B23 = LCELL( _EQ022);
  _EQ022 =  s3 & !s5 & !s8
         # !s3 &  s5 & !s8;

-- Node name is ':252' 
-- Equation name is '_LC3_B23', type is buried 
_LC3_B23 = LCELL( _EQ023);
  _EQ023 =  _LC8_B20
         #  _LC2_B23 &  _LC8_B23 & !s2;

-- Node name is '~253~1' 
-- Equation name is '~253~1', location is LC6_B16, type is buried.
-- synthesized logic cell 
!_LC6_B16 = _LC6_B16~NOT;
_LC6_B16~NOT = LCELL( _EQ024);
  _EQ024 = !_LC5_B20
         #  s1
         #  s2 &  s3
         # !s2 & !s3;

-- Node name is ':253' 
-- Equation name is '_LC1_B16', type is buried 
_LC1_B16 = LCELL( _EQ025);
  _EQ025 =  _LC8_B21
         #  _LC6_B16;

-- Node name is '~254~1' 
-- Equation name is '~254~1', location is LC3_B16, type is buried.
-- synthesized logic cell 
_LC3_B16 = LCELL( _EQ026);
  _EQ026 =  _LC3_B20 &  s1 & !s2
         #  _LC4_B16;

-- Node name is ':254' 
-- Equation name is '_LC8_B21', type is buried 
_LC8_B21 = LCELL( _EQ027);
  _EQ027 =  _LC3_B16
         #  _LC1_B23;



Project Information                                    f:\vhdl\qdq\decoder.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,896K