example6-8.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 13 行

LIBRARY IEEE;
ENTITY test IS END;
ARCHITECTURE example OF test IS
  SIGNAL s : INTEGER := 0;
BEGIN
  PROCESS
    BEGIN
      s <= REJECT 5ns INERTIAL 3 AFTER 1ns, 5 AFTER 3ns,
            6 AFTER 5ns, 8 AFTER 6ns, 6 AFTER 8ns, 7 AFTER 15ns;
      s <= REJECT 5ns INERTIAL 6 AFTER 9ns, 10 AFTER 18ns;
      WAIT;
    END PROCESS;
END example;