example6-3.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
END test;
ARCHITECTURE example OF test IS
  SIGNAL s1, s2 : Std_ULogic;
BEGIN
p1: PROCESS
  BEGIN
    s1 <= '1' AFTER 15ns;
    s1 <= '0' AFTER 10ns;
    WAIT;
  END PROCESS p1;
p2: PROCESS
  BEGIN
    s2 <= '1' AFTER 15ns;
    WAIT FOR 15ns;
    s2 <= '0' AFTER 10ns;
    WAIT FOR 10ns;
    WAIT;
  END PROCESS p2;
END ARCHITECTURE example;