example6-9.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT (in1, in2, in3 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
BEGIN
  PROCESS
  BEGIN
    out1 <= NOT in1;
    WAIT ON in2 UNTIL in2 = '1';
  END PROCESS;
END ARCHITECTURE example;
ARCHITECTURE temp OF test IS
BEGIN
  PROCESS
  BEGIN
    WAIT ON in2 UNTIL in2 = '1';
out1 <= NOT in1;
  END PROCESS;
END ARCHITECTURE temp;