example6-10.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 13 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT (in1, in2 : IN Std_Logic := '1';
        out1 : INOUT Std_Logic := '1';
        out2 : INOUT Std_Logic := '0');
END ENTITY test;
ARCHITECTURE example OF test IS
BEGIN
  out1 <= in2 NAND out2;
  out2 <= in1 NAND out1;
END ARCHITECTURE example;