example4-23.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 14 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT ( reset : IN Std_Logic := '0');
BEGIN
  ASSERT reset = '1'
REPORT "Reset Active!" SEVERITY ERROR;
END ENTITY test;
ARCHITECTURE example OF test IS
BEGIN
  ASSERT FALSE
  REPORT "Example message" SEVERITY NOTE;
END ARCHITECTURE example;