example4-31.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 15 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  GENERIC (tp_lh, tp_hl : TIME);
  PORT (in1, in2 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
  SIGNAL temp : Std_Logic;
BEGIN
  temp <= in1 OR in2;
  out1 <= temp AFTER tp_lh WHEN temp = '1' ELSE
          temp AFTER tp_hl;
END ARCHITECTURE example;