example4-30.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  GENERIC (n : INTEGER := 8);
  PORT (in1 : IN Std_Logic_Vector (n DOWNTO 1);
        in2 : IN Std_Logic_Vector (n DOWNTO 1);
        in3 : IN Std_Logic;
        out1 : OUT Std_Logic_Vector (n DOWNTO 1);
        out2 : OUT Std_Logic);
END test;
ARCHITECTURE example OF test IS
  COMPONENT adder
    PORT (in1 : IN Std_Logic;
          in2 : IN Std_Logic;
          in3 : IN Std_Logic;
          out1 : OUT Std_Logic;
          out2 : OUT Std_Logic);
  END COMPONENT;
  SIGNAL temp : Std_Logic_Vector (1 TO n-1);
BEGIN
  gen1 : FOR i IN 1 TO n GENERATE
    gen2 : IF i = 1 GENERATE
      U1 : adder PORT MAP (in1(i), in2(i), in3, out1(i), temp(i));
    END GENERATE gen2;
    gen3 : IF i > 1 AND i < n GENERATE
      U2 : adder PORT MAP (in1(i), in2(i), temp (i-1), out1(i), temp(i));
    END GENERATE gen3;
    gen4 : IF i = n GENERATE
      U3 : adder PORT MAP (in1(n), in2(n), temp (n-1), out1(n), out2);
    END GENERATE gen4;
  END GENERATE gen1;
END example;