example4-20.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test IS
  PORT ( a, b : IN Std_Logic;
           c : OUT Std_Logic);
END ENTITY test;
ARCHITECTURE example OF test IS
BEGIN
b1 : BLOCK
  PORT (a, b : IN Std_Logic;
        s, c : OUT Std_Logic);
  PORT MAP (a, b, s, c);
  BEGIN
    p1 : PROCESS (a, b)
    BEGIN
      s <= a XOR b;
    END PROCESS p1;
    p2 : PROCESS (a, b)
    BEGIN
      c <= a AND b;
    END PROCESS p2;
  END BLOCK b1;
END ARCHITECTURE example;