example4-32.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY test2 IS
  GENERIC (tp_lh, tp_hl : TIME);
  PORT (in1, in2, in3, in4 : IN Std_Logic;
        out1 : OUT Std_Logic);
END test2;
ARCHITECTURE example2 OF test2 IS
  COMPONENT test
    GENERIC (tp_lh, tp_hl : TIME);
    PORT (in1, in2 : IN Std_Logic;
          out1 : OUT Std_Logic);
  END COMPONENT;
  SIGNAL temp1, temp2 : Std_Logic;
BEGIN
  U1: test GENERIC MAP (4ns, 3ns) PORT MAP (in1, in2, temp1);
  U2: test GENERIC MAP (4ns, 3ns) PORT MAP (in3, in4, temp2);
  U3: test GENERIC MAP (8ns, 6ns) PORT MAP (temp1, temp2, out1);
END ARCHITECTURE example2;