example4-21.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 13 行

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY guardedr IS
  PORT (d, clk : IN Std_Logic;
        q : OUT Std_Logic);
END guardedr;
ARCHITECTURE example OF guardedr IS
BEGIN
  b1 : BLOCK (clk = '1')
  BEGIN
    q <= GUARDED d AFTER 5 ns;
  END BLOCK b1;
END ARCHITECTURE example;