example4-29.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY half_adder IS
  GENERIC(tpd : TIME := 10 ns);
  PORT(in1, in2: IN Std_Logic;
sum, carry: OUT Std_Logic);
END half_adder;
ARCHITECTURE behavioral OF half_adder IS
BEGIN
  PROCESS(in1, in2)
  BEGIN
    sum <= in1 XOR in2 AFTER tpd;
    carry <= in1 AND in2 AFTER tpd;
  END PROCESS;
END behavioral;
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY or_gate IS
  GENERIC(tpd : TIME := 10 ns);
  PORT(in1, in2: IN Std_Logic;
out1: OUT Std_Logic);
END or_gate;
ARCHITECTURE structural OF or_gate IS
BEGIN
  out1 <= in1 OR in2 AFTER tpd;
END structural;
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY full_adder IS
  GENERIC(tpd: TIME := 10 ns);
  PORT(x, y, c_in: IN Std_Logic;
sum, c_out: OUT Std_Logic);
END full_adder;
ARCHITECTURE structural OF full_adder IS
  COMPONENT half_adder
    PORT(in1, in2: IN Std_Logic;
sum, carry: OUT Std_Logic);
END COMPONENT;
  COMPONENT or_gate
    PORT(in1, in2: IN Std_Logic;
out1: OUT Std_Logic);
END COMPONENT;
SIGNAL a, b, c: Std_Logic;
FOR u1, u2: half_adder USE ENTITY Work.half_adder(behavioral);
FOR u3: or_gate USE ENTITY Work.or_gate(structural);
BEGIN
  u1: half_adder PORT MAP(x, y, b, a);
  u2: half_adder PORT MAP(c_in, b, sum, c);
  u3: or_gate PORT MAP(c, a, c_out);
END structural;