example4-18.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY syn IS 
  PORT(in1, clk : IN Std_Logic;
        out1 : OUT Std_Logic);
END syn;
ARCHITECTURE behavioral OF syn IS
BEGIN
  p1 : PROCESS (clk)
  BEGIN
    IF clk = '1' THEN
      out1 <= in1 AFTER 10 ns;
    END IF;
  END PROCESS p1;
END behavioral;