example14-8.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY compactor IS
	PORT(
ap:OUT std_logic_vector(15 downto 0);
		RSTbar:IN std_logic;
		number:IN integer range 0 TO 255);
END compactor;

ARCHITECTURE behave OF compactor IS
BEGIN
	PROCESS(number,RSTbar)
		VARIABLE compactout:std_logic_vector(15 downto 0);
		VARIABLE compactin:integer range 0 TO 255;
	BEGIN
		IF RSTbar='1' THEN
			compactout:="0000000000000000";
		ELSE
			compactin:=number;
			IF compactin >255 THEN compactout:="1111111111111111";
			ELSIF compactin >196 THEN compactout:="0111111111111111";
			ELSIF compactin >169 THEN compactout:="0011111111111111";
			ELSIF compactin >144 THEN compactout:="0001111111111111";
			ELSIF compactin >121 THEN compactout:="0000111111111111";
			ELSIF compactin >100 THEN compactout:="0000011111111111";
			ELSIF compactin >81  THEN compactout:="0000001111111111";
			ELSIF compactin >64  THEN compactout:="0000000111111111";
			ELSIF compactin >49  THEN compactout:="0000000011111111";
			ELSIF compactin >36  THEN compactout:="0000000001111111";
			ELSIF compactin >25  THEN compactout:="0000000000111111";
			ELSIF compactin >16  THEN compactout:="0000000000011111";
			ELSIF compactin >9   THEN compactout:="0000000000001111";
			ELSIF compactin >4   THEN compactout:="0000000000000111";
			ELSIF compactin >1   THEN compactout:="0000000000000011";
			ELSIF compactin>0    THEN compactout:="0000000000000001";
			ELSE	compactout:="0000000000000000";
			END IF;
			ap<=compactout;
		END IF;
	END PROCESS;
END behave;