example14-14.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY alu_unit IS
	PORT (
		op1: IN STD_LOGIC;
		op2: IN STD_LOGIC;
		cin: IN STD_LOGIC;
		y: IN STD_LOGIC_VECTOR (3 downto 0);
		carry_control: IN STD_LOGIC;
		sum: OUT STD_LOGIC;
		cout: BUFFER STD_LOGIC
		);
END alu_unit;

ARCHITECTURE behave OF alu_unit IS
	COMPONENT mux4_1
		PORT(
			a:in std_logic;
			b:in std_logic;
			y:in std_logic_vector(3 downto 0);
			f:out std_logic
			);
	END COMPONENT;
	COMPONENT chain
		PORT(
			cin:in std_logic;
			kill:in std_logic;
			propagate:in std_logic;
			carry_control:in std_logic;
			cout:buffer std_logic
			);
	END COMPONENT;
	SIGNAL half:std_logic;
	SIGNAL q:std_logic;
	SIGNAL kill:std_logic;
BEGIN
	func:mux4_1 PORT MAP (op1,op2,y,q);
	carry_chain:chain PORT MAP (cin,kill,half,carry_control,cout);
	half<=not q;
	kill<=( not op2 ) and ( not half );
	sum<=half xor cin;	
END behave;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY mux4_1 IS
	PORT(
		a:in std_logic;
		b:in std_logic;
		y:in std_logic_vector(3 downto 0);
		f:out std_logic
		);
END mux4_1;

ARCHITECTURE behave OF mux4_1 IS
BEGIN
	PROCESS(a,b,y)
		VARIABLE sel:std_logic_vector(1 downto 0);
	BEGIN
		sel:=b & a;
		CASE sel IS
			WHEN "00"=>f<=y(0);
			WHEN "01"=>f<=y(1);
			WHEN "10"=>f<=y(2);
			WHEN "11"=>f<=y(3);
			WHEN others=>NULL;
		END CASE;
	END PROCESS;
END behave;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY chain IS
	PORT(
		cin:in std_logic;
		kill:in std_logic;
		propagate:in std_logic;
		carry_control:in std_logic;
		cout:buffer std_logic
		);
END chain;

ARCHITECTURE behave OF chain IS
BEGIN
	PROCESS(cin,kill,propagate,carry_control)
	BEGIN
		IF carry_control='1' THEN
			cout<='1';
		ELSE
			IF kill='1' THEN
				cout<='1';
			ELSIF propagate='1' THEN
				cout<=cin;
			ELSE
				cout<='1';
			END IF;
		END IF;
	END PROCESS;
END behave;