example14-12.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

ENTITY fetch IS
	PORT (
		clk: IN std_logic;
		reset: IN std_logic;
		refresh: IN std_logic;
		rom_ready: IN std_logic;
		is_1byte: IN std_logic;
		is_2byte: IN std_logic;
		fifo_datao: IN std_logic_vector (7 downto 0);
		new_PC:IN std_logic_vector(15 downto 0);
		int_req:IN std_logic;
		indir:IN std_logic;
		get_dat:IN std_logic;
		wr_bak:IN std_logic;
		end_intr:IN std_logic;
		end_ins:IN std_logic;
		dec_discard: OUT std_logic;
		opcode: OUT std_logic_vector (7 downto 0);
		byte1: OUT std_logic_vector (7 downto 0);
		byte2: OUT std_logic_vector (7 downto 0)
		);
END fetch;

ARCHITECTURE behave OF fetch IS
	CONSTANT RD_OPCODE:std_logic_vector:="000";
	CONSTANT RD_BYTE1:std_logic_vector:="001";
	CONSTANT RD_BYTE2:std_logic_vector:="011";
	CONSTANT FETCH_IND:std_logic_vector:="010";
	CONSTANT FETCH_DAT:std_logic_vector:="111";
	CONSTANT EXE_INS:std_logic_vector:="110";
	CONSTANT WR_BACK:std_logic_vector:="100";
	CONSTANT INTERR:std_logic_vector:="101";
	SIGNAL Q_exe_ctl:std_logic_vector(2 downto 0);
	SIGNAL D_exe_ctl:std_logic_vector(2 downto 0);
	SIGNAL DAT_EXE:std_logic_vector(2 downto 0);
	SIGNAL NXT_STP:std_logic_vector(2 downto 0);
	SIGNAL PC:std_logic_vector(15 downto 0);
	
BEGIN
	--****************************************************************
	--*             Control of read instrunciton					 *
	--****************************************************************
	--assignment
	DAT_EXE<=FETCH_DAT WHEN get_dat='1' ELSE EXE_INS;
	NXT_STP<=FETCH_IND WHEN indir='1' ELSE DAT_EXE;
	--****************************************************************
	PROCESS(Q_exe_ctl,rom_ready,is_1byte,is_2byte,NXT_STP,DAT_EXE,end_ins,wr_bak,end_intr)
	BEGIN
		D_exe_ctl<=Q_exe_ctl;
		CASE Q_exe_ctl IS
			WHEN RD_OPCODE=>
			IF int_req='1' THEN
				D_exe_ctl<=INTERR;
			ELSIF rom_ready='1' THEN
				IF is_2byte='1' THEN
					D_exe_ctl<=NXT_STP;
				ELSE
					D_exe_ctl<=RD_BYTE1;
				END IF;
			END IF;
			WHEN RD_BYTE1=>
			IF rom_ready='1' THEN
				IF is_2byte='1' THEN
					D_exe_ctl<=NXT_STP;
				ELSE
					D_exe_ctl<=RD_BYTE2;
				END IF;
			END IF;
			WHEN RD_BYTE2=>
			IF rom_ready='1' THEN
				D_exe_ctl<=NXT_STP;	
			END IF;				   
			WHEN FETCH_IND=>
			D_exe_ctl<=DAT_EXE;
			WHEN FETCH_DAT=>
			D_exe_ctl<=EXE_INS;
			WHEN EXE_INS=>
			IF end_ins='1' THEN
				IF wr_bak='1' THEN
					D_exe_ctl<=WR_BACK;
				ELSE
					D_exe_ctl<=RD_OPCODE;
				END IF;
			END IF;
			WHEN WR_BACK=>
			D_exe_ctl<=RD_OPCODE;
			WHEN INTERR=>
			IF end_intr='1' THEN
				D_exe_ctl<=RD_OPCODE;
			END IF;	
			WHEN others=>NULL;
		END CASE;
	END PROCESS;
	--****************************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF reset='1' THEN
				Q_exe_ctl<=RD_OPCODE;
			ELSE
				IF refresh='1' THEN
					Q_exe_ctl<=RD_OPCODE;
				ELSE
					Q_exe_ctl<=D_exe_ctl;
				END IF;
			END IF;
		END IF;
	END PROCESS;
	--Latch instruction
	--****************************************************************
	PROCESS(Q_exe_ctl,fifo_datao)
	BEGIN
		IF (Q_exe_ctl=RD_OPCODE) THEN
			opcode<=fifo_datao;
		END IF;
	END PROCESS;
	--****************************************************************
	PROCESS(Q_exe_ctl,fifo_datao)
	BEGIN
		IF (Q_exe_ctl=RD_BYTE1) THEN
			byte1<=fifo_datao;
		END IF;
	END PROCESS;
	--****************************************************************
	PROCESS(Q_exe_ctl,fifo_datao)
	BEGIN
		IF (Q_exe_ctl=RD_BYTE2) THEN
			byte2<=fifo_datao;
		END IF;
	END PROCESS; 
	--program count***************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF reset='1' THEN
				PC<=(others=>'0');
			ELSIF rom_ready='1' THEN
				PC<=PC+"0000000000000001";
			ELSIF (refresh='1' and Q_exe_ctl=WR_BACK) THEN
				PC<=new_PC;
			END IF;
		END IF;
	END PROCESS;
END behave;