example14-10.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY interface IS
	PORT (
		clk: IN std_logic;
		reset: IN std_logic;
		exe_io_ext: IN std_logic;
		exe_wr_ext: IN std_logic;
		exe_rd_eprom: IN std_logic;
		fifo_rd_ext: IN std_logic;
		exe_datao_ext: IN std_logic_vector (7 downto 0);
		aPC: IN std_logic_vector (15 downto 0);
		exe_addr_ext: IN std_logic_vector (15 downto 0);
		ALE: OUT std_logic;
		nPSEN: OUT std_logic;
		nRD: OUT std_logic;
		nWR: OUT std_logic;
		ext_fifo_ack: OUT std_logic;
		ext_exe_ack: OUT std_logic;
		CADDR: OUT std_logic_vector (7 downto 0);
		ext_datai: OUT std_logic_vector (7 downto 0);
		ADR_DAT: INOUT std_logic_vector (7 downto 0)
		);
END interface;

ARCHITECTURE behave OF interface IS
	SUBTYPE STATE_TYPE IS integer range 0 to 3;
	CONSTANT EXT_IDLE:STATE_TYPE:=0;
	CONSTANT RD_EPROM0:STATE_TYPE:=1;
	CONSTANT RD_EPROM1:STATE_TYPE:=2;
	CONSTANT IO_RAM:STATE_TYPE:=3;
	SIGNAL Q_ext:STATE_TYPE;
	SIGNAL D_ext:STATE_TYPE;
	SIGNAL end_rd_eprom:std_logic;
	SIGNAL end_io_ram:std_logic;
	SIGNAL ext_step:std_logic_vector(3 downto 0);
	SIGNAL rd_eprom:std_logic;
	SIGNAL do_io:std_logic;
	
BEGIN
	-- allocate time slot process
	PROCESS(Q_ext,exe_io_ext,exe_rd_eprom,fifo_rd_ext,end_rd_eprom,end_io_ram)
	BEGIN
		D_ext<=Q_ext;
		CASE Q_ext IS
			WHEN EXT_IDLE =>
			IF exe_io_ext='1' THEN
				IF exe_rd_eprom ='1' THEN
					D_ext<=RD_EPROM1;
				ELSE
					D_ext<=IO_RAM;
				END IF;
			ELSIF fifo_rd_ext='1' THEN
				D_ext<=RD_EPROM0;
			END IF;
			WHEN RD_EPROM0=>
			IF end_rd_eprom='1' THEN
				IF exe_io_ext='1' THEN
					IF exe_rd_eprom='1' THEN
						D_ext<=RD_EPROM1;
					ELSE
						D_ext<=IO_RAM;
					END IF;
				ELSIF fifo_rd_ext='0' THEN
					D_ext<=EXT_IDLE;
				END IF;
			END IF;
			WHEN RD_EPROM1=>
			IF end_rd_eprom='1' THEN
				IF fifo_rd_ext='1' THEN
					D_ext<=RD_EPROM0;
				ELSE
					D_ext<=EXT_IDLE;
				END IF;
			END IF;
			WHEN IO_RAM=>
			IF end_io_ram='1' THEN
				IF fifo_rd_ext='1' THEN
					D_ext<=RD_EPROM0;
				ELSE
					D_ext<=EXT_IDLE;
				END IF;
			END IF;	
		END CASE;
	END PROCESS;
	--****************************************************************
	PROCESS(clk,reset)
	BEGIN
		IF reset='1' THEN
			Q_ext<=EXT_IDLE;
		ELSE
			Q_ext<= D_ext;
		END IF;
	END PROCESS;
	--*****************************************************************
	PROCESS(Q_ext)
	BEGIN
		IF Q_ext=RD_EPROM0 or Q_ext=RD_EPROM1 THEN
			rd_eprom<='1';
		ELSE			
			rd_eprom<='0';
		END IF;
		IF Q_ext=IO_RAM THEN
			do_io<='1';
		ELSE
			do_io<='0';
		END IF;
	END PROCESS;
	--*******************************************************************	
	--access external eprom processes
	PROCESS(ext_step,rd_eprom,do_io)
	BEGIN
		IF (ext_step="0101" and rd_eprom='1') THEN
			end_rd_eprom<='1';
		ELSE
			end_rd_eprom<='0';
		END IF;
		IF ext_step="1011" and do_io='1' THEN
			end_io_ram<='1';
		ELSE
			end_io_ram<='0';
		END IF;		
	END PROCESS;
	--*********************************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF Q_ext=EXT_IDLE THEN
				ext_step<="1111";
			ELSIF (end_rd_eprom='1' or end_io_ram='1') THEN
				ext_step<="0000";
			ELSE
				ext_step<=ext_step+"0001";
			END IF;
		END IF;
	END PROCESS;
	--**********************************************************************
	PROCESS(end_rd_eprom,ADR_DAT,ext_step)
		VARIABLE addr_enable:std_logic;
		VARIABLE addr_sel:std_logic_vector(15 downto 0);
		VARIABLE step01:std_logic;
		VARIABLE rd_wr:std_logic;
	BEGIN
		IF (end_rd_eprom='1' or ext_step="1000") THEN
			ext_datai<=ADR_DAT;
		END IF;
		IF (ext_step="0001" or ext_step="0010") THEN
			addr_enable:='1';
		END IF;
		IF Q_ext=RD_EPROM0 THEN
			addr_sel:=aPC;
		ELSE
			addr_sel:=exe_addr_ext;
		END IF;
		CADDR<=addr_sel(15 downto 8);
		IF addr_enable='1' THEN
			ADR_DAT<=addr_sel(7 downto 0);
		ELSIF do_io='1' and exe_wr_ext='1' THEN
			ADR_DAT<=exe_datao_ext;
		ELSE
			ADR_DAT<=(others=>'Z');
		END IF;
		IF((end_rd_eprom='1' and Q_ext=0) or Q_ext=1) THEN
			ext_fifo_ack<='1';
		ELSE
			ext_fifo_ack<='0';
		END IF;
		IF (((end_rd_eprom='1' and Q_ext=2) or Q_ext=3) or end_io_ram='1') THEN
			ext_exe_ack<='1';
		ELSE
			ext_exe_ack<='0';
		END IF;
		IF ext_step="0000" or ext_step="0001" THEN
			step01:='1';
		ELSE
			step01:='0';
		END IF;
		IF (step01='1' and (Q_ext/=EXT_IDLE)) THEN
			ALE<='1';
		ELSE
			ALE<='0';
		END IF;
		IF ((step01='1' or ext_step="0010") or rd_eprom='0') THEN
			nPSEN<='1';
		ELSE
			nPSEN<='0';
		END IF;
		IF ((ext_step="0101" or ext_step="0110") or ext_step="0111" or ext_step="1000" or ext_step="1001" or ext_step="1010")THEN
			rd_wr:='1';
		ELSE
			rd_wr:='0';
		END IF;
		IF do_io='0' or rd_wr='0' or exe_wr_ext='1' THEN
			nRD<='1';
		ELSE
			nRD<='0';
		END IF;
		IF do_io='0' or rd_wr='0' or exe_wr_ext='0' THEN
			nWR<='1';
		ELSE
			nWR<='0';
		END IF;		
	END PROCESS;
	--**********************************************************************
END behave;