example14-11.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;

ENTITY fifo IS
	PORT (
		clk: IN std_logic;
		reset: IN std_logic;
		dec_discard: IN std_logic;
		ext_fifo_ack: IN std_logic;
		sack0: IN std_logic;
		refresh: IN std_logic;
		use_cache: IN std_logic;
		ext_datai: IN std_logic_vector (7 downto 0);
		sdatai: IN std_logic_vector (7 downto 0);
		new_PC: IN std_logic_vector (15 downto 0);
		cache_start: IN std_logic_vector (15 downto 0);
		cache_len: IN std_logic_vector (7 downto 0);
		sreq0: OUT std_logic;
		fifo_rd_ext: OUT std_logic;
		fifo_ready: OUT std_logic;
		fifo_datao: OUT std_logic_vector (7 downto 0);
		saddr0: INOUT std_logic_vector (8 downto 0);
		aPC: INOUT std_logic_vector (15 downto 0)
		);
END fifo;

ARCHITECTURE behave OF fifo IS
	CONSTANT RD_EXT_INS:std_logic:='0';
	CONSTANT RD_SRAM_INS:std_logic:='1';
	SIGNAL Q_rd_ins:std_logic;
	SIGNAL D_rd_ins:std_logic;
	SIGNAL refresh_f:std_logic;
	SIGNAL fifo_full:std_logic;
	SIGNAL in_fresh:std_logic;
	SIGNAL is_ack:std_logic;
	SIGNAL next_aPC:std_logic_vector(15 downto 0);
	SIGNAL diff:std_logic_vector(15 downto 0);
	SIGNAL hit:std_logic;
	SIGNAL putin:std_logic;
	SIGNAL fifo_1:std_logic_vector(7 downto 0);
	SIGNAL fifo_2:std_logic_vector(7 downto 0);
	SIGNAL fifo_3:std_logic_vector(7 downto 0);
	SIGNAL fifo_cnt:std_logic_vector(2 downto 0);
	SIGNAL nxt_cnt:std_logic_vector(2 downto 0);
	SIGNAL putin0:std_logic;
	SIGNAL putin1:std_logic;
	SIGNAL putin2:std_logic;
	SIGNAL putin3:std_logic;
	SIGNAL data_in:std_logic_vector(7 downto 0);
	
BEGIN
	--advanced program counter and read instruction ahead
	--assignment*******************************************************
	in_fresh<='1' WHEN (refresh='1' or refresh_f='1') ELSE '0';
	is_ack<='1' WHEN (ext_fifo_ack='1' or sack0='1') ELSE '0';
	next_aPC<=new_PC WHEN in_fresh='1' ELSE	(aPC+"0000000000000001");
	diff<=(aPC-cache_start) WHEN Q_rd_ins='1' ELSE (next_aPC-cache_start);
	saddr0<=diff(8 downto 0);
	hit<='1' WHEN ((diff(15 downto 9)="0000000" ) and (saddr0<=cache_len) and (use_cache='1')) ELSE	'0';
	putin<='1' WHEN (is_ack='1' and in_fresh='0') ELSE '0';
	sreq0<='1' WHEN (fifo_full='0' and Q_rd_ins=RD_SRAM_INS) ELSE '0';
	fifo_rd_ext<='1' WHEN (fifo_full='0' and (Q_rd_ins=RD_EXT_INS) and ext_fifo_ack='0') ELSE '0';
	--******************************************************************
	PROCESS(Q_rd_ins,hit,ext_fifo_ack,sack0)
	BEGIN
		D_rd_ins<=Q_rd_ins;
		CASE Q_rd_ins IS
			WHEN RD_EXT_INS=>
			D_rd_ins<=RD_SRAM_INS;
			WHEN RD_SRAM_INS=>
			IF (hit='0' and sack0='1') THEN
				D_rd_ins<=RD_EXT_INS;
			END IF;
			WHEN others=>NULL;
		END CASE;
	END PROCESS;
	--******************************************************************
	PROCESS(clk,reset)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF (reset='1') THEN
				Q_rd_ins<=RD_EXT_INS;
			ELSE
				Q_rd_ins<=D_rd_ins;
			END IF;
		END IF;
	END PROCESS;
	--******************************************************************
	PROCESS(clk,reset)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF (reset='1') THEN
				refresh_f<='0';
			ELSIF is_ack='1' THEN
				refresh_f<='0';
			ELSIF refresh='1' THEN
				refresh_f<='1';
			END IF;
		END IF;
	END PROCESS;
	--******************************************************************
	PROCESS(clk,reset)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF (reset='1') THEN
				aPC<=(others=>'0');
			ELSE
				aPC<=next_aPC;
			END IF;
		END IF;
	END PROCESS;
	--******************************************************************
	--fifo processes
	--assignment********************************************************
	nxt_cnt<=fifo_cnt+"001";
	fifo_full<='1' WHEN ((fifo_cnt(2)='1' or nxt_cnt(2)='1') and ext_fifo_ack='1') ELSE '0';
	putin0<='1' WHEN (putin='1' and fifo_cnt="000") ELSE '0';
	putin1<='1' WHEN (putin='1' and fifo_cnt="001") ELSE '0';
	putin2<='1' WHEN (putin='1' and fifo_cnt="010") ELSE '0';
	putin3<='1' WHEN (putin='1' and fifo_cnt="011") ELSE '0';
	data_in<=sdatai WHEN hit='1' ELSE ext_datai;
	--*******************************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF reset='1' THEN
				fifo_cnt<="000";
			ELSIF refresh='1' or refresh_f='1' THEN
				fifo_cnt<="000";
			ELSE
				IF (dec_discard='1' and putin='0' and fifo_cnt/="000") THEN
					fifo_cnt<=fifo_cnt-"001";
				END IF;
				IF (dec_discard='1' and putin='1' and fifo_cnt(2)='0') THEN
					fifo_cnt<=nxt_cnt;
				END IF;
			END IF;
		END IF;
	END PROCESS;
	--*******************************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF dec_discard='1' THEN
				IF putin1='1' THEN
					fifo_datao<=data_in;
				ELSE
					fifo_datao<=fifo_1;
				END IF;
			ELSIF putin0='1' THEN
				fifo_datao<=data_in;
			END IF;
		END IF;
	END PROCESS;
	--*******************************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF dec_discard='1' THEN
				IF putin2='1' THEN
					fifo_1<=data_in;
				ELSE
					fifo_1<=fifo_2;
				END IF;
			ELSIF putin0='1' THEN
				fifo_1<=data_in;
			END IF;
		END IF;
	END PROCESS;
	--*******************************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF dec_discard='1' THEN
				IF putin3='1' THEN
					fifo_2<=data_in;
				ELSE
					fifo_2<=fifo_3;
				END IF;
			ELSIF putin0='1' THEN
				fifo_2<=data_in;
			END IF;
		END IF;
	END PROCESS;
	--*******************************************************************
	PROCESS(clk)
	BEGIN
		IF clk'EVENT and clk='1' THEN
			IF putin3='1' THEN
				fifo_3<=data_in;
			END IF;
		END IF;
	END PROCESS;
	--*******************************************************************	
END behave;