example14-3.vhd

vhdl 实例 通过实例学习vhdl 编程

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;

ENTITY dram IS
	GENERIC(read_delay,write_delay,cas_delay,ras_delay,dis_delay:time);
	PORT (
		addr: IN STD_LOGIC_vector (9 downto 0);
		data: INOUT STD_LOGIC_vector (7 downto 0);
		ras: IN STD_LOGIC;
		cas: IN STD_LOGIC;
		we: IN STD_LOGIC
		);
END dram;

ARCHITECTURE behave OF dram IS
	SUBTYPE DRAM_RANGE IS integer range 0 to 524287;
	SUBTYPE MEMORY_DATA IS std_logic_vector(7 downto 0);--8 bit data
	TYPE MEMORY IS array (0 to 524287) OF MEMORY_DATA;--dram array
	SIGNAL address_full:std_logic_vector(18 downto 0);--19 bit address bus
	SIGNAL dram_array :MEMORY;
	SIGNAL address:std_logic_vector(9 downto 0);
--function	definition
	FUNCTION logic2int(din: std_logic_vector(18 downto 0)) RETURN DRAM_RANGE IS
		VARIABLE result:DRAM_RANGE:=0;
	BEGIN
		FOR i IN 0 TO 18 LOOP
			IF din(i)='1' THEN
				result:=result+2**i;
			END IF;
		END LOOP;
		RETURN result;
	END FUNCTION logic2int;	
BEGIN
	get_address:PROCESS(ras)
	BEGIN
		IF ras'EVENT and ras='0' THEN
			address<= addr after ras_delay;
		END IF;
	END PROCESS get_address;
	
	main:PROCESS(cas,we)
		VARIABLE intaddr: integer;
	BEGIN
		IF cas'EVENT and cas='0' THEN
			address_full<=(address & addr(8 downto 0)) after cas_delay;
		END IF;
		intaddr:=logic2int(address_full);
		IF we='0' and cas='0' and ras='0' THEN
			dram_array(intaddr)<=data after write_delay; 
		ELSIF we='1' and cas='0' and ras='0' THEN
			data<=dram_array(intaddr) after read_delay;
		ELSIF cas'EVENT and cas='1' THEN
			data<=(others=>'Z') after dis_delay;
		END IF;
	END PROCESS main;	
END behave;