example14-2.vhd

来自「vhdl 实例 通过实例学习vhdl 编程」· VHDL 代码 · 共 52 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

PACKAGE ram_pack IS
	SUBTYPE RAM_WORD IS std_logic_vector(7 downto 0);
	SUBTYPE RAM_RANGE IS integer range 0 to 31;
	TYPE RAM_TYPE IS array (RAM_RANGE) OF RAM_WORD;
END ram_pack;

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.ram_pack.all;

ENTITY ram IS
	GENERIC(read_delay:time);
	PORT (
		clk: IN STD_LOGIC;
		data: INOUT STD_LOGIC_VECTOR (7 downto 0);
		addr: IN std_logic_vector(4 downto 0);
		cs: IN STD_LOGIC;
		read: IN STD_LOGIC;
		write: IN STD_LOGIC
		);
END ram;

ARCHITECTURE behave OF ram IS
	SIGNAL memory: RAM_TYPE;
	FUNCTION logic2int(din: std_logic_vector(4 downto 0)) RETURN RAM_RANGE IS
		VARIABLE result:RAM_RANGE:=0;
	BEGIN
		FOR i IN 0 TO 4 LOOP
			IF din(i)='1' THEN
				result:=result+2**i;
			END IF;
		END LOOP;
		RETURN result;
	END FUNCTION logic2int;
BEGIN
	PROCESS(read,write,cs,addr,data)
	BEGIN
		IF cs='0' THEN
			IF read='1' THEN
				data<=memory(logic2int(addr)) after read_delay;
			ELSIF write='1' THEN
				memory(logic2int(addr))<=data;
			END IF;
		ELSE
			data<=(others=>'Z');
		END IF;
	END PROCESS;		   
END behave;